IC-MD_17 Datasheet, PDF (12/30 Pages) IC-Haus GmbH – 48-BIT QUADRATURE COUNTER

iC-MD 48-BIT QUADRATURE COUNTE^pR^reliminary
WITH RS422 RECEIVER AND SPI/BISS INTERFACE
COUNTER CONFIGURATION
Rev B1, Page 12/30
iC-MD has a 48 bit counter configurable from single to
up to three counters with bit lengths from 16 to 48 bit.
Table 13 show all the possible counters configuration
considering table 18 and table 20.
The ”count of counter” configuration is given by the
registers CNTCFG as shown in table 13.
If it is configured with more than one counter, the
input stage must be set to TTL (table 17).
CNTCFG
Code
000
001
010
011
100
101
110
111
Addr. 0x00; bit (2:0)
Default = 0b000
Counter Configuration
CNT0 = 24 bit: 1 counter: TTL, RS422 or LVDS
CNT0 = 24 bit + CNT1 = 24 bit:2 counter: TTL only
CNT0 = 48 bit: 1 counter: TTL, RS422 or LVDS
CNT0 = 16 bit: 1 counter: TTL, RS422 or LVDS
CNT0 = 32 bit: 1 counter: TTL, RS422 or LVDS
CNT0 = 32 bit + CNT1 = 16 bit: 2 counter: TTL only
CNT0 = 16 bit + CNT1 = 16 bit: 2 counter: TTL only
CNT0 = 16 bit + CNT1 = 16 bit + CNT2 = 16 bit:
3 counter: TTL only
Table 13: Count of Counter and Counter Length Con-
figuration
Note that the three counter configuration does not
implement any Zero signal input, only A and B in-
put signals.
The 48 bit register of the AB counter is also used as
"SPI data channel" for data exchanging between SPI
and BiSS interface, for that purpose the bit CH0SEL
(table 65) must be set to 1. When CH0SEL = 1, the
counting function for all the counters is deactivated.
Index Signal Z
In default operation configuration, the index signal Z
is active when A = B = 1, as shown in table 14 with
EXCH = 0 and INVZ = 0. All other configurations are
also possible.
CFGZ
Code
00
01
10
11
Addr. 0x01; bit (4:3)
Function:
Z active: when A = 1 B = 1
Z active: when A = 1 B = 0
Z active: when A = 0 B = 1
Z active: when A = 0 B = 0
Default = 0b00
Table 14: Index Signal Configuration
It can also be deactivated the clearing of counter by the
index signal with the configuration bit CBZ ( table 15
and table 16 ).
The CBZ configuration is only applicable after the sec-
ond index pulse after power-on or the activation of
ZCEN (table 40), because after it, the iC-MD will reset
the counter value by the firsts two index pulse, indepen-
dently of the CBZ configuration, in order to have the AB
Counter value referenced to the second index pulse.
By default, CBZ is set to 0, also the counters are not
reset to 0 by the index signal. But the firsts two Index
pulse always reset the counters.
CBZ0
Code
0
1
Addr. 0x01; bit (5)
Function
CNT0 not cleared by Z0 signal
CNT0 cleared by Z0 signal
Default = 0b0
Table 15: CNT0 Cleared By Z0 Signal
CBZ1
Code
0
1
Addr. 0x01; bit (6)
Function
CNT1 not cleared by Z1 signal
CNT1 cleared by Z1 signal
Default = 0b0
Table 16: CNT0 Cleared By Z1 Signal