IC-MD_17 Datasheet, PDF (21/30 Pages) IC-Haus GmbH – 48-BIT QUADRATURE COUNTER

iC-MD 48-BIT QUADRATURE COUNTE^pR^reliminary
WITH RS422 RECEIVER AND SPI/BISS INTERFACE
STATUS0 (Addr. 0x48)
Update Register Valid
AB CNT0 decodification error
READ
READ
NS
C
Q
D _NQ
NS
C
Q
D
NQ
0 TPVAL
1 OVFREF
UPDVAL
3
RVAL
4 PDWN
5 ZERO0
6 OVF0
ABERR0
STATUS1 (Addr. 0x49)
AB CNT1 decodification error
READ
NS
C
Q
D
NQ
0
TPS
1 COMCOL
2 EXTWARN
3 EXTERR
4 PDWN
5 ZERO1
6 OVF1
ABERR1
STATUS2 (Addr. 0x4A)
0 ENSSI
1 COMCOL
2 EXTWARN
3 EXTERR
4 PDWN
AB CNT2 decodification error
READ
NS
C
Q
5 ZERO2
6 OVF2
ABERR2
1
D
NQ
Configuration (Addr. 0x03)
0 MASK(8)
1 MASK(9)
2 NMASK(0)
3 NMASK(1)
4
5
6
7
LVDS
Figure 9: NMASK gating
&
Other
mask bits
&
Other
mask bits
Rev B1, Page 21/30
1
NWARN
Pin and
NWARN in measurement data
1
NERR
Pin and
NERR in measurement data
The latched events are reset with reading the STATUS addresses 0x48, 0x49 or 0x4A unless the event signals do
not persist. The read access is indicated by the latch reset signal ”READ”.
MASK
Bit
9
8
7
6
5*
4
3
2
1
0
Notes
Adr 0x02, bit 7:0; Adr 0x03, bit 1:0 Default = 0x000
Error/Warning Event
enable SSI (warning)
external error (error)
zero value of active counter 0, 1 or 2 (warning)
touch-probe valid (warning)
power down (RAM was initialized) (warning)
overflow of reference counter (warning)
overflow of counter 0, 1 or 2 (warning)
REF reg. valid (warning)
external warning (warning)
register communication collision (warning)
encoding of bit 9 . . . 0:
0 = message disabled, 1 = message enabled
Table 57: Error/Warning Event Masks
NMASK
Bit
1
0
Notes
Adr 0x03, bit 3:2 Default = 0b00
error/warning event
AB decodification error. e.g. too high
frequency(error)
UPD reg. valid (warning)
encoding of bit 1...0:
0 = message enabled, 1 = message disabled
Table 58: Error/Warning Event Not Masks