IC-MD_17 Datasheet, PDF (14/30 Pages) IC-Haus GmbH – 48-BIT QUADRATURE COUNTER

iC-MD 48-BIT QUADRATURE COUNTE^pR^reliminary
WITH RS422 RECEIVER AND SPI/BISS INTERFACE
24 BIT REFERENCE COUNTER
Rev B1, Page 14/30
An additional 24 bit counter is integrated in order to load
the REF and UPD registers. The value of this internal
counter can not be read, it can only be read the values
of REF and UPD registers. The reference counter is
activated by default after power-on and reset with every
index signal (it is not affected by the configuration bit
CFGZ, table 14).
Since the internal counter for REF and UPD is 24 bit
long, the maximum number of edges that can be eval-
uated (loaded in UPD and REF) between two index
signal goes from -2²³ (negative counting direction) to
2²³-1 (positive counting direction).
REF REGISTER
After the start up (Power on), the iC-MD counts the
number of edges between the first two different index
signals (Z) in the register REF. This function is always
activated by the following situations:
- after power-on.
- by activating the zero codification function via instruc-
tion byte (table 40).
of edges between the first two index signals stored in
REF.
REF(23:0)
Addr. 0x10 to 0x12;
R
REF register value
0xXXXXXX
Table 26: Reference Counter Value
The process runs as following: the "reference counter"
is set to zero with the first index signal, and the second
index signal (must be different of the first one) loads the
register REF with the value of "reference counter". It
is the distance between the first and the second index
signals. The AB counter is then set to 0 with the second
index signal. The counter value is then referenced to
the position of the second Z signal, and the number
After the second index signal, the status bit RVAL (table
48) is set and remains at this value until the next power
on, the activation of the zero codification function or
until the resetting of the counter 0.
The following diagrams show the reference position ac-
quisition process also called as zero codification func-
tion.
Figure 4: Zero-Codification: REF and UPD registers after activation of Zero Codification function