IC-MD_17 Datasheet, PDF (16/30 Pages) IC-Haus GmbH – 48-BIT QUADRATURE COUNTER

iC-MD 48-BIT QUADRATURE COUNTE^pR^reliminary
WITH RS422 RECEIVER AND SPI/BISS INTERFACE
TP1, TP2 and AB REGISTERS
Rev B1, Page 16/30
TP1, TP2 Registers
The touch probe registers consist of two 24 bit registers
which are load with a TPI pin event (see table 29) or
writing the instruction bit TP (table 41) via SPI/BiSS. At
every TPI pin or TP instruction event, the register TP2
is load with the value of TP1 and TP1 is load with the
actual value of counter 0. For using TP registers, AB
counter must be configured to 24 bit, but if 2x24 bit coun-
ters are configured, only the counter 0 will be latched
into TP1/TP2 registers. The TPI pin events can be
configured as falling, rising or both edges, as shown in
table 29.
TPCFG
Code
00
01
10
11
Addr. 0x01; bit (2:1)
Function
both edges active
rising edge active
falling edge active
pin TPI disabled
Default = 0b00
Table 29: TPI Pin Configuration
TP1(23:0)
Addr. 0x0C;
R
TP1 value
0xXXXXXX
Table 30: Touch Probe 1
TP2(23:0)
Addr. 0x0E;
R
TP2 value
0xXXXXXX
Table 31: Touch Probe 2
NTPVAL
Addr. 0x0C or 0x0E;
R
0
TP valid
1
TP not valid
Table 32: Touch Probe Register Not Valid
The following diagram (figure 7) shows the function of
the pin TPI when configured for both rising and falling
edge.
Figure 7: Function of TPI pin when TPCFG=11
AB Register
NERR
Addr. 0x08;
R
A 48 bit register (AB) is used to store and shift out the 0
Error active
ABCNT Registers (Counters), and also the "SPI Chan- 1
No Error active
nel Data" (SPICH). The register AB is read via BiSS
(sensor data, channel 0) or via SPI (Adr 0x08), and the
Table 35: No Error
bit length is set by the configuration bits CNTCFG (table
13)
NABERR
Addr. 0x0A or 0x0C or
R
0x0E;
AB(47:0)
Addr. 0x08;
0xXX..XX AB counter value
R
0
1
AB counter value error
AB counter correct value
Table 33: AB Counter Values
Table 36: No AB Counter Error
NWARN
0
1
Addr. 0x08;
Warning active
No warning active
Table 34: No Warning
R The bit CH0SEL (table 65) selects the data to be load
in the AB register when reading the channel 0 via BiSS
or the address 0x08 via SPI.