IC-MD_17 Datasheet, PDF (22/30 Pages) IC-Haus GmbH – 48-BIT QUADRATURE COUNTER

iC-MD 48-BIT QUADRATURE COUNTE^pR^reliminary
WITH RS422 RECEIVER AND SPI/BISS INTERFACE
SPI INTERFACE
Rev B1, Page 22/30
The Serial Peripheral Interface (SPI) of iC-MD consists
of a SPI slave interface with polarity 0 and phase 0.
mand defines the operations to be performed
(Write/Read) and the address.
Each transmission starts with a falling edge of NCS
and ends with the rising edge. During transmission,
commands and data are controlled by SCK and NCS
according to the following rules:
• Commands and data are shifted; MSB first, LSB
last
• Each output data/status bits are shifted out on the
falling edge of SCK (MISO line) and each bit is
sampled on the rising edge of SCK (Polarity 0,
Phase 0).
• After the device is selected with the falling edge
of NCS, an 8-bit command is received. The com-
• The rising edge of NCS ends all data transfer and
resets internal counter and command register
• Data transfer out from MISO starts with the falling
edge of SCK immediately after the last bit of the
SPI command is sampled in on the rising edge of
SCK
• Data transfer to MOSI continues immediately after
receiving the command in all cases where data is
to be written to iC-MD internal registers
• The SPI interface can not be used for daisy chain
setups.
SPI Communication
The first byte to be transmitted to the iC-MD via SPI is the instruction (or command) which determine the
communication direction (read or write), and has the following structure:
Bit 7
R/W
Bit 6
Bit 5
SPI Commands
Bit 4
Bit 3
Bit 2
ADDRESS(6:0)
Table 59: SPI command structure
Bit 1
Bit 0
The following diagrams show the SPI write and read
processes.
NCS
SCLK
MOSI
MISO
0
ADR(6:0)
Polarity 0, Phase 0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
X
Byte to write in ADR
Byte to write in ADR+1
High Impedance
Figure 10: SPI Write Data
NCS
SCLK
MOSI
MISO
1
ADDRESS(6:0)
High Impedance
Polarity 0, Phase 0
don't care
n
n-1
n-2
n-3
n-4
n-5
Figure 11: SPI Read Data
5
4
3
2
1
0
X High Impedance