IC-MD_17 Datasheet, PDF (18/30 Pages) IC-Haus GmbH – 48-BIT QUADRATURE COUNTER

iC-MD 48-BIT QUADRATURE COUNTE^pR^reliminary
WITH RS422 RECEIVER AND SPI/BISS INTERFACE
STATUS REGISTER and ERROR/WARNING INDICATION
Rev B1, Page 18/30
The three bytes status registers (Adr. 0x48 to 0x4A)
indicate the state of the iC-MD. All the status bits are
latched (except TPS) when an error/warning occurs
and are reset when reading the error/warning via SPI
or BiSS excepts RVAL. The status bits TPVAL and UP-
DVAL are also reset by reading the register TP1 and
UPD respectively.
ZEROx
Code
0
1
Notes
Addr. 0x48, 0x49, 0x4A;
R
bit 5
Description
no zero of counter x
zero of counter x
x = 0, 1, 2
reset by reading Adr. 0x48 (ZERO0), 0x49 (ZERO1)
and 0x4A (ZERO2)
The status bit TPS (table 55) is not latched, it signals
the actual state of the input pin TPI.
Table 46: Zero Value in Counter CNTx
Two of this status bits are error bits; ABERR (AB decod-
ification error, table 44) and EXTERR (external error,
table 52), all others status bits signal warnings.
If VDD reaches the power off supply level (VDDoff,
Spec. Item No. 602), the iC-MD is reset and the RAM
initialized to the default value. Status bit PDWN indi-
cates that this initialization has taken place.
Status bits ABERRx indicate a decodification error of
the AB inputs, it occurs if the counting frequency is too
high or if two incremental edges are too close (PHab2,
Spec. Item No.303).
ABERRx
Code
0
1
Notes
Addr. 0x48, 0x49, 0x4A;
R
bit 7
Description
No decodification error in counter x
Decodification error in counter x
x = 0, 1, 2
Reset by reading Adr. 0x48 (ABERR0),
0x49 (ABERR1) and
0x4A (ABERR2)
The corresponding counter must be reset (ABRES)
after an error
Table 44: AB Decodification Error of Counter CNTx
The maximum counting range of the counters depends
on the counter configuration (see table 13). A counter
with the bit length "n" has the maximum counting range
will be from -2^n-1 up to 2^n-1-1. The corresponding bit
OVFx is set to 1 if the counter exceeds these values.
OVFx
Code
0
1
Notes
Addr. 0x48, 0x49, 0x4A;
R
bit 6
Description
no overflow in counter x
overflow in counter x
x = 0, 1, 2
reset by reading Adr. 0x48 (OVF0), 0x49 (OVF1)
and 0x4A (OVF2)
PDWN
Addr. 0x48, 0x49, 0x4A;
R
bit 4
Code
Description
0
No undervoltage
1
Undervoltage(RAM was reset)
Notes
Reset by reading Adr. 0x48, 0x49 or 0x4A
Table 47: Undervoltage Reset
RVAL status bit indicates that the reference value was
load in the REF register, after the "Zero Codification"
process. After power-on, this bit remains at 0 until the
second different Index pulse.
RVAL
Code
0
1
Notes
Addr. 0x48; bit 3
R
Description
REF Reg. not valid
REF Reg. valid
Reset by the instruction ZCEN(see table 40)
Table 48: REF Register Values Valid
Every time that the UPD register is loaded, the status
bit UPDVAL (UPD valid) is set to 1 until the status bit
UPD or the register UPD is read via SPI or BiSS.
UPDVAL
Code
0
1
Notes
Addr. 0x48; bit 2
R
Description
UPD Reg. not valid
UPD Reg. valid
Reset by reading Adr. 0x48 or the register UPD via
SPI (Adr. 0x0A) or BiSS (Channel 1)
Table 45: Counter Overflow Warning of Counter CNTx
Table 49: UPD Register Values Valid
ZEROx bits indicate that the counter value has reached If the number of AB edges between two index sig-
the zero value.
nals is greater than 2²³-1=8388607 or lower than