IC-MD_17 Datasheet, PDF (20/30 Pages) IC-Haus GmbH – 48-BIT QUADRATURE COUNTER

iC-MD 48-BIT QUADRATURE COUNTE^pR^reliminary
WITH RS422 RECEIVER AND SPI/BISS INTERFACE
Error and warning mask
Rev B1, Page 20/30
The masks (MASK) and not masks (NMASK) bits, stipulate whether error and warning events are signaled as an
alarm via the open drain I/O pins NERR and NWARN.
NERR pin forced
READ
NS
C
Q
D
NQ
NWARN pin forced
READ
NS
C
Q
D _NQ
STATUS1 (Addr. 0x49)
0
TPS
1 COMCOL
EXTWARN
EXTERR
4 PDWN
5 ZERO1
6 OVF1
7 ABERR1
STATUS2 (Addr. 0x4A)
0 _ENSSI
1 COMCOL
EXTWARN
EXTERR
4 PDWN
5 ZERO2
6
OVF2
7 ABERR2
Configuration (Addr. 0x02)
0 MASK(0)
1 MASK(1)
2 MASK(2)
3 MASK(3)
4 MASK(4)
5 MASK(5)
6 MASK(6)
7 MASK(7)
Configuration (Addr. 0x03)
0 MASK(8)
1 MASK(9)
2 NMASK(0)
3 ^NMASK(1)
4
5
6
7
LVDS
Figure 8: MASK gating
&
Other
mask bits
&
Other
mask bits
1
NERR
Pin and
NERR in measurement data
1
NWARN
Pin and
NWARN in measurement data
The latched events are reset with reading the STATUS addresses 0x48, 0x49 or 0x4A unless the event signals do
not persist. The read access is indicated by the latch reset signal ”READ”.