IC-MD_17 Datasheet, PDF (19/30 Pages) IC-Haus GmbH – 48-BIT QUADRATURE COUNTER

iC-MD 48-BIT QUADRATURE COUNTE^pR^reliminary
WITH RS422 RECEIVER AND SPI/BISS INTERFACE
Rev B1, Page 19/30
-2²³=-8388608 the status bit OVFREF is set to 1 and
indicates that the value of the UPD and REF registers
are not valid.
OVFREF
Addr. 0x48; bit 1
R
Code
Description
0
No Overflow in reference counter
1
Overflow in reference counter
Notes
Reset by reading Adr. 0x48
Table 50: Reference Counter Overflow
After loading TP1/TP2 register, either via pin TPI or
instruction TP (see table 41), the bit TPVAL is set to
1 and remains at 1 until the reading of TPVAL, TP1 or
TP2 via SPI or BiSS.
EXTWARN
Addr. 0x49, 0x4A; bit 2
R
Code
Description
0
no external warning
1
external warning
Notes
reset by reading Adr. 0x49 or 0x4A
Table 53: External Warning
If BiSS/SSI and SPI try to access at the same time
to the internal data bus (BiSS register communication
and SPI communication) the bit COMCOL will be set
indicating that a collision has taken place. If SPICH is
activated (table 65), the writing process of AB via SPI
and reading of channel 0 via BiSS at the same time will
generate no COMCOL warning.
If a communication collision take place, only the inter-
face with priority (See table 71) executes the write/read
process correctly, but the other interface doe not write
any data, the other interface does read a false value.
TPVAL
Addr. 0x48; bit 0
R
COMCOL
Addr. 0x49, 0x4A; bit 1
R
Code
Description
Code
Description
0
1
Notes
TPx registers not loaded
TP1 and TP2 registers have not been updated
New values loaded in TP1 and TP2
Reset by reading Adr. 0x48, register TP1 or register
0
1
Notes
no communication collision
communications collided
reset by reading Adr. 0x49 or 0x4A
TP2 via SPI (Adr. 0x0C and 0x0E) or BiSS (channel
1 and channel 2, see table 65)
Table 54: Communication Collision
Table 51: Touch Probe Values Valid
The status bit (EXTERR: external error) indicates if the
pin NERR was either pulled-down from outside or set to
0 from inside (an internal masked error has occurred).
Bit TPS signals the actual state of the input pin TPI. If
the pin TPI is high, the bit TPS remains at 1, and if TPI
is set to low, TPS status bit is 0.
TPS
Addr. 0x49; bit 0
R
Code
Description
0
TPI pin at low
1
TPI pin at high
EXTERR
Code
0
1
Notes
Addr. 0x49, 0x4A; bit 3
Description
no external error
external error
Reset by reading Adr. 0x49 or 0x4A
Table 52: External Error
R
Table 55: Touch-Probe Pin Status
Status bit ENSSI signals if the SSI interface instead of
BiSS is configured. This is configured by the SLI pin, if
the pin is open, the SSI interface is selected. ENSSI
has an internal digital filter of 25 µs maximum.
ENSSI
Addr. 0x4A; bit 0
R
Code
Description
The status bit (EXTWARN: external warning) bit indi- ⁰
cates if the pin NWARN was either pulled-down from ¹
SSI not enabled
SSI enabled (pin SLI open)
outside or set to 0 from inside (an internal masked
warning has occurred).
Table 56: SSI Enabled