IC-MD_17 Datasheet, PDF (26/30 Pages) IC-Haus GmbH – 48-BIT QUADRATURE COUNTER

iC-MD 48-BIT QUADRATURE COUNTE^pR^reliminary
WITH RS422 RECEIVER AND SPI/BISS INTERFACE
BiSS Device ID Addr. 0x78 0x79; bit
(7,0)
0x78
0x4D = ASCII "M"
0x79
0x44 = ASCII "D"
Table 68: BiSS Device ID
Rev B1, Page 26/30
R
BiSS Device
Addr. 0x7E 0x7F; bit
R
Manufacturer ID (7,0)
0x7E
0x69 = ASCII "i"
0x7F
0x43 = ASCII "C"
Table 70: BiSS Device Manufacturer ID
BiSS Device ID Addr. 0x7A. . . 0x7D; bit
R
(7,0)
0x7A
0x5A = ASCII "Z" iC-MD Redesign Z
0x7B
. . . 0x7D
0x00 = ASCII n.a. (first redesign)
0x7A
0x5A = ASCII "Z" iC-MD Redesign Z1
0x7B
0x31 = ASCII "1"
0x7C
. . . 0x7D
0x00 = ASCII n.a.
0x7A
0x59 = ASCII "Y" iC-MD Redesign Y
0x7B
. . . 0x7D
0x00 = ASCII n.a.
0x7A
0x58 = ASCII "X" iC-MD Redesign X
0x7B
. . . 0x7D
0x00 = ASCII n.a. (latest redesign)
Table 69: BiSS Device ID, BiSS Device Revision
SSI Protocol
An SSI protocol is selected if the input pin SLI is open.
This enable signal has an internal digital filter of 25 µs
maximum.
A clock pulse train from a controller is used to gate out
sensor data. Between each clock pulse train there is a
SSI timeout during which fresh data is moved into the
register. Data is shifted out when the iC-MD receives
a pulse train from the controller. When the least sig-
nificant bit (LSB) goes high after the SSI timeout, new
data is available to read.
The AB counter data transmitted is in the form of a
binary code (24 bit + NERR + NWARN). If the input MA
continues being clocked without SSI timeout, it will be
output a total of 94 bit with the following scheme:
Figure 12: Output data with SSI protocol
INTERFACE PRIORITY
The Configuration bit PRIOR (Adr. 0x03, bit 1), set
which interface has priority when taking place a Read-
/Write interface collision. It means that if BiSS and SPI
try to access to the configuration register at the same
time, then only the one with the priority will write/read
successfully the register. The error in the interface with-
out priority will be signalized by the collision Status bit:
SPICOL or BISSCOL, Adr.0x4A, bit(1:0).
SPI Channel: SPI to BiSS communication
The counter register is also used for the transmission of
data from SPI to BiSS. The data exchanging take place
as following:
1. SPI writes the data to be transmitted in address
0x20 to 0x25, this data is written in the counter
registers. The data length to be transmitted is
selected by CNTCFG (Table 13) and can be con-
figured as 16, 24, 32 or 48-bit
PRIOR
Code
0
1
Addr. 0x03; bit 0
Function
BiSS priority
SPI priority
Default = 0b0
Table 71: SPI Interface Priority
2. After the writing process, the bit SPICHVAL is set
to 1 and read via BiSS as Warning bit of channel
0.
3. BiSS reads out the channel 0, the data written
via SPI and two status bits, NERR and NWARN
which indicates if the read data is valid.