IC-MD_17 Datasheet, PDF (2/30 Pages) IC-Haus GmbH – 48-BIT QUADRATURE COUNTER

iC-MD 48-BIT QUADRATURE COUNTE^pR^reliminary
WITH RS422 RECEIVER AND SPI/BISS INTERFACE
Rev B1, Page 2/30
DESCRIPTION
iC-MD evaluates incremental encoder signals with A,
B and index tracks from up to three encoders.
After power-on the iC-MD has all the RAM bits at 0 as
default configuration, that means one 24 bit counter
is configured with RS422 differential inputs. The en-
coder signals A+/A- are connected to AP,AN, B+/B-
to BP,BN and Z+/Z- to CP,CN. The device can be
programmed via the SPI interface or BiSS Interface.
The 48 bit counter can be configured as up to three
counters with variable counter depths of 16, 24, 32
or 48 bits, but the sum of bits of all the configured
counters can not be higher than 48 bits. Some of the
possible configurations are 1x48 bit, 2x24 bit, 3x16 bit,
1x32 + 1x16 bit. Each edge of the synchronized en-
coder signal counts (fourfold edge evaluation).
An additional 24bit counter REF counter is used to
store the distance (number of pulses) between the
first two index pulses after power-on and the distance
between every last two index pulses in UPD register.
An event at the input pin TPI (configurable as rising,
falling or both edges) loads the register TP1 with the
actual value of the counter 0, and shift the old value
of TP1 in register TP2. This registers can also be
loads through the instruction bit TP, via SPI or BiSS
(Register communication).
Two bidirectional ports are used as error and warning
output (low active) and can be pulled down from out-
side to signals an external error or external warning.
This external error and warning are internally latched
in the status registers.
A set of status registers monitor the status of the
counter, TP1, TP2, REF, UPD, power on and external
error and warning pins.
The BiSS Interface uses the BiSS C protocol and
reads out the counter and registers TP1, TP2 and
UPD as Sensor data. REF register is read via BiSS C
register communication.
The device described here is a multifunctional iC that contains
integrated BiSS C interface components. The BiSS C process is
protected by patent DE 10310622 B4 owned by iC-Haus GmbH
and its application requires the conclusion of a license (free of
charge).
Download the license at
www.biss-interface.com/bua