IC-JX_16 Datasheet, PDF (45/48 Pages) IC-Haus GmbH – 16-FOLD 24 V HIGH-SIDE DRIVER

iC-JX
16-FOLD 24 V HIGH-SIDE DRIVER WITH µC INTERFACE
SPI: Writing single/multiple data to an iC-JX
Rev C2, Page 45/48
NCS
D0/SI
D1/SOC
D2/SOB
StartAdr
StartAdr
-transparent-
NoB
0x0F
NoB
0x0F
NoB
0x0F
EndAdr
Control Byte
( = StartAdr)
0x59
Figure 19: SPI: Writing a single register value
NCS
D0/SI
D1/SOC
D2/SOB
StartAdr
StartAdr
-transparent-
NoB
NoB
NoB
Figure 20: SPI: Writing several register values
In the write process one or several registers can be writ-
ten during a transmit cycle (see Fig. 19 and 20). To this
end the master first sends the start address (addressing
sequence see Fig. 16) and the numerical amount of
data to be transmitted minus one (NoB, see Tab. 22).
As in the read process this value is transmitted as two
nibbles (non-inverted and inverted) to increase secu-
rity. Data from consecutive addresses is then sent by
the master. iC-JX returns the master data with a delay
of one byte, allowing the master to constantly monitor
whether an error has occurred during the addressing
sequence or data transmission. If an error is detected,
the master can prevent the faulty data being accepted
by the slave registers by ending communication.
SPI: Error handling
In order to reduce processing time complex technology,
such as CRC, etc., is not used for error handling. The
transmitted addresses and data are instead returned
by the recipient to the sender where they are compared
to the original data transmitted.
Should the master detect an error, it can abort commu-
nication in such a way so as to prevent incorrect values
being written to the slaves.
If an individually addressed slave determines that the
data it has sent has been returned to it incorrectly or
that the number of clock pulses is not a multiple of 8
bits, it can signal this error to the master by inverting
the closing control byte.