IC-JX_16 Datasheet, PDF (38/48 Pages) IC-Haus GmbH – 16-FOLD 24 V HIGH-SIDE DRIVER

iC-JX
16-FOLD 24 V HIGH-SIDE DRIVER WITH µC INTERFACE
Stage 1:
no
temperature > Toff1?
yes
Interrupt Status Register A:
● _{IET1 interrupt}
● _{ET1 set}
no
temperature < Ton1?
yes
Interrupt Status Register A:
● _{ET1 reset}
Stage 2:
no
temperature > Toff2?
yes
Interrupt Status Register A:
● _{IET2 interrupt}
● _{ET2 set}
I/O stages:
● _{pull-up/downs disabled}
● _{Output-Register A/B reset}
● _{Flash Pulse Enable A/B reset}
Note:
take measures to
decrease power
dissipation
Note:
this disables the output
transistors of the I/O
stages
no
temperature < Ton2?
yes
Interrupt Status Register A:
● _{ET2 reset}
I/O stages:
● _{pull-up/downs re-enabled}
Note:
Output-Register A/B,
Flash Pulse Enable A/B
must be reconfigured
Figure 11: Two-stage temperature monitor circuit (for
Toff1/2, Ton1/2 refer to Elec. Char.)
Rev C2, Page 38/48
Note:
Should the supply voltage at VCC or VDD rise to VC-
Con or VDDon after undervoltage detection, all regis-
ters of iC-JX except the interrupt bits IUSA, IUSD and
ISD in Interrupt Status Register B have been reset.
Undervoltage detection: VB1...4
In order to guarantee the fail-safe operation of con-
nected loads voltages VB1..4 are also monitored.
If one of the voltages VBy (y=1..4) drops below thresh-
old VByoff (see Elec. Char. I02) the output transistors
of the corresponding I/O Nibble are disabled. Once volt-
age VBy again rises above VByon (see Elec. Char. I01)
the output transistors of the corresponding I/O Nibble
are re-enabled.
Note that neither a device reset nor an interrupt mes-
sage to the microcontroller are then triggered. The
microcontroller can read out the status of the voltages
VB1..4 at bit USVB in the Device ID register (Addr.
0x1D, P. 30). In the event of error (one of the voltages
VB1..4 < VByoff) this bit is set to 1.
Pin monitoring GNDD and GNDA
iC-JX includes a pin watchdog circuit which monitors
the connection between the two ground pins GNDA and
GNDD. The microcontroller can detect a possible error,
such as a disconnected IC lead, for example, by read-
ing bit IBA in the Interconnection Error register (Addr.
0x1D, P. 30). In the event of error IBA is set to 1.
Undervoltage detection: VCC and VDD
When the supply voltage at VCC or VDD is switched on
the output transistors of IO1..16 configured as outputs
are only enabled by the undervoltage detector after
power-on enables VCCon or VDDon (see Elec. Char.
501) have been reached.
Should the supply voltage drop below VCCoff or VDDoff
(see Elec. Char. 502) during operation, interrupt bits
IUSA (for VCC) or IUSD (for VDD) are set in Interrupt
Status Register B (Addr. 0x05, P. 29). The I/O stages
are disabled, i.e. the output transistors are turned off.
All registers and the Interrupt Status Register A/B ex-
cept the interrupt bits IUSA, IUSD and ISD are reset.
Statusbits USD and USA statically indicate undervolt-
age at VDD and VCC.
Note:
If such a case of an error is present (disconnected IC
lead), then the potential of the missing ground pin is
raised, which can lead to a shift of the trigger levels.
Burst detection at VDD
As in principle bursts at VDD can influence the contents
of registers iC-JX monitors spikes in the supply. If any
hazard is detected Bit ISD is set to 1 in the Interrupt Sta-
tus Register B (Addr. 0x05, P. 29). The I/O stages are
disabled, i.e. the output transistors are turned off. All
registers and the Interrupt Status Register A/B except
the interrupt bits IUSA, IUSD and ISD are reset.
Stored interrupt message ISD and the display at NINT
resp. D1/SOC or D2/SOB can be deleted by setting
EOI to 1 in Control Word 4 (Addr. 0x1A, P. 21).
Stored interrupt messages IUSD and IUSA and the dis-
play at NINT resp. D1/SOC or D2/SOB can be deleted
by setting EOI to 1 in Control Word 4 (Addr. 0x1A, P.
21).
Note:
After burst detection at VDD the registers of iC-JX are
reset except the interrupt bits IUSA, IUSD and ISD in
Interrupt Status Register B.