IC-JX_16 Datasheet, PDF (43/48 Pages) IC-Haus GmbH – 16-FOLD 24 V HIGH-SIDE DRIVER

iC-JX
16-FOLD 24 V HIGH-SIDE DRIVER WITH µC INTERFACE
SPI: Setting address of an iC-JX
Rev C2, Page 43/48
NCS
A3/SCLK
D0/SI
BA1 BA0 RA4 RA3 RA2 RA1 RA0 RNW
BA1..0:Device address
RA4..0:Register address
RNW: Read/not Write
D1/SOC
BA1 BA0 RA4 RA3 RA2 RA1 RA0 RNW
SI switched to SOC
- transparent-
D2/SOB
Figure 16: SPI: Addressing sequence
The first byte of communication (see Fig. 16) consists device ID is set for each chip using pins A(1:0). In chain
of the 2-bit chip address (BA1:0), the 5-bit register ad- configuration up to four devices can thus be connected
dress (RA4:0) and a read-not-write (RNW) bit. The to a SPI master.
SPI: Reading single data from an iC-JX
NCS
D0/SI
D1/SOC
StartAdr
StartAdr
-transparent-
NoB
0x0F
Control Byte
0x59
D2/SOB
Figure 17: SPI: Reading a single register value
The following describes the SPI data transmission for
a single read access (see Fig. 17). The first byte sent
by the controller (master) is the address the data is to
be read out from (addressing sequence see Fig. 16).
The activated iC-JX (slave) sends the address back in
the next byte by way of verification while the master
sends a NOP (0x00) byte. The slave then sends the
required data. The master sends byte NoB which is the
number of bytes to be read out minus one. To increase
security the number byte NoB is split into two nibbles
which are encoded with the original and inverted value
(0x0F when reading 1 byte, see Tab. 22).
If the user does not need the verification mechanisms
of the master and the slave to validate the sent data,
the master may terminate the read cycle at this point.
The master otherwise sends the received data back to
the slave which then returns the address of the read
register (in this instance the start address) by way of
verification. If this does not match the one originally
sent by the master, the master can then abort com-
munication and repeat if necessary. If the address is
correct, in the next stage of the procedure the master
transmits the control byte optimized for maximum error
recognition (0x59).
For its part the slave checks that the returned data is
correct; if this is so, it then also transmits the control
byte 0x59. In the event of error an inverted value of
0xA6 is sent. During the transmission of this control
byte the slave also checks whether the signals at SI
and SOC/SOB are synchronous. If this is not the case
(due to a spike occurring at SCK, for example), the
slave transmits the inverted control byte as soon as it
has detected the error.