IC-JX_16 Datasheet, PDF (37/48 Pages) IC-Haus GmbH – 16-FOLD 24 V HIGH-SIDE DRIVER

iC-JX
16-FOLD 24 V HIGH-SIDE DRIVER WITH µC INTERFACE
Rev C2, Page 37/48
generates a ’1’ at bit INx in the Input Register A/B. A
low at IOx generates a ’0’ at bit INx.
Once the Change-of-input Message has been enabled
in the Change-of-input Interrupt Enable register (Addr.
0x10 and 0x11, P. 28) a change of level at one of the
I/O pins is signaled to the microcontroller. Interrupt pin
NINT is set to 0. If the device is operated at the serial
interface a change of level is also indicated by a 1 at
pin D1/SOC or D2/SOB, depending upon configuration
(see SPI interface, Tab. 20, P. 42). The microcon-
troller can determine which I/O stage has had a change
of input by reading out the Change-of-input Message
Register A/B (Addr. 0x02 and 0x03, P. 25).
Overcurrent messages
If an overload occurs at one of the outputs the current
in IOx is limited. In this instance an interrupt message
is triggered, providing relevant interrupt enables have
been set for overcurrent messages (Addr. 0x12 and
0x13, P. 28) and the filter time set with Control Word
4 (Addr. 0x1A, P. 21) has elapsed. ISCI is then set in
the Interrupt Status Register (Addr. 0x04, P. 29) and
the relevant bit for the I/O stage causing the problem
is set in the Overcurrent Message register (Addr. 0x06
and 0x07, P. 26). Filtering of the overcurrent message
can be shut down using a bypass; this bypass can be
activated for all I/O stages together using BYPSCF in
Control Word 4 (Addr. 0x1A, P. 21).
Note:
If during operation an I/O nibble is switched from input
to output mode, all Change-of-input Messages of the
corresponding I/O nibble are deleted.
I/O stages configured as output: monitor logic
level status
As with the reading of inputs the feedback signals of
outputs can be output in their filtered or unfiltered state.
The microcontroller can determine the actual status of
the I/O stages by reading out Input Register A/B (Addr.
0x00 and 0x01, P. 25). A high at IOx generates a ’1’ at
bit INx in the Input Register A/B. A low at IOx generates
a ’0’ at bit INx.
This allows the microcontroller to make a direct check
of the switching state and, with the help of the pro-
grammable high-side current sources of 200 µA, 600 µA
and 2 mA, to monitor the channel for any cable break
before an output is switched on with the Output Register
(P. 24).
IOx
iC-JX
cable break ↯
configure output and
pull-up current for IOx
(Control Word 2A/B)
At addresses 0x08 and 0x09 (see P. 26) the actual,
unfiltered overcurrent status of each I/O stage can be
read; a global scan of all I/O stages is also possible via
bit SCS in the Interrupt Status Register. This shows
whether any of the I/O stages have overcurrent at the
time of the readout. This short-circuit messaging al-
lows permanent monitoring of the output transistors
and clear allocation of error message to affected I/O
stages.
Temperature monitoring
iC-JX has a two-stage temperature monitor circuit (see
Fig 11).
Stage 1: A warning interrupt IET1 is generated if the
first temperature threshold (Toff1 at approx. 132 °C)
is exceeded. Suitable measures to decrease the
power dissipation of the driver can be implemented
using the microcontroller.
Stage 2: If the second temperature threshold is ex-
ceeded (Toff2 at approx. 152 °C), a second interrupt
IET2 is generated. At the same time the I/O stage
pull-up and pull-down current sources are disabled
and the registers Output-Register A/B and Flash
Pulse Enable A/B are reset to disable the output
transistors. Once the temperature has returned to
below the level of Ton2 (approx. 132 °C) the pul-
l-up and pull-down current sources are reactivated.
Output-Register A/B and Flash Pulse Enable A/B
have to be configured anew to reactivate the output
stages
Read Pin Status: logic level
(Input Register A/B)
logic level 1?
yes
no
enable outputs
(Output Register A/B)
cable break ↯
Figure 10: Monitor cable break
Status bits ET1 and ET2 statically indicate when Toff1
and Toff2 are exceeded. Interrupt messages IET1 and
IET2 as well as the status bits ET1 and ET2 can be
read at Interrupt Status Register A (Addr. 0x04, P. 29).
Stored interrupt message IET1 and IET2 and the dis-
play at NINT resp. D1/SOC or D2/SOB can be deleted
by setting EOI to 1 in Control Word 4 (Addr. 0x1A, P.
21).