IC-JX_16 Datasheet, PDF (4/48 Pages) IC-Haus GmbH – 16-FOLD 24 V HIGH-SIDE DRIVER

iC-JX
16-FOLD 24 V HIGH-SIDE DRIVER WITH µC INTERFACE
PACKAGING INFORMATION MQFP52 to JEDEC Standard
Rev C2, Page 4/48
PIN CONFIGURATION MQFP52, pitch 0.65 mm
NRD
1
NWR
2
NCS
3
VCC
4
NSP
5
GNDA ⁶
RSET ⁷
A3 / SCK ⁸
A1
9
D7
10
D5
11
D3
12
D1 / SOC ¹³
iC-JX Code...
...
...yyww
39 CLK
38 GNDD
37 BLFQ
36 NRES
35 VDD
34 A4
33 A2
32 A0
31 D6
30 D4
29 D2 / SOB
28 _{D0 / SI}
27 _NINT
PIN FUNCTIONS
No. Name Function
1 NRD Not Read Enable
2 NWR Not Write Enable
3 NCS Not Chip Select
4 VCC Supply Voltage (analog, 3...5.5 V)
5 NSP Not Serial / Parallel (Mode)
6 GNDA Ground (analog)
7 RSET Resistor Setting (10 kΩ)
8 A3 Address Bus
9 A1 Address Bus
10 D7 Data Bus
11 D5 Data Bus
12 D3 Data Bus
13 D1 Data Bus
14 POE Power Output Enable
15 GNDA Ground (analog)
16 IO16 I/O Stage 16
17 IO15 I/O Stage 15
18 VB4 Supply Voltage for I/O Stages 13...16
19 IO14 I/O Stage 14
20 IO13 I/O Stage 13
21 IO12 I/O Stage 12
PIN FUNCTIONS
No. Name Function
22 IO11 I/O Stage 11
23 VB3 Supply Voltage for I/O Stages 9...12
24 IO10 I/O Stage 10
25 IO9 I/O Stage 9
26 GNDA Ground (analog)
27 NINT Not Interrupt
28 D0 Data Bus
29 D2 Data Bus
30 D4 Data Bus
31 D6 Data Bus
32 A0 Address Bus
33 A2 Address Bus
34 A4 Address Bus
35 VDD Supply Voltage (logic, 3...5.5 V)
36 NRES Not Reset
37 BLFQ Blink Frequency
38 GNDD Ground (logic)
39 CLK Clock (optional)
40 GNDA Ground (analog)
41 IO1 I/O Stage 1
42 IO2 I/O Stage 2
43 VB1 Supply Voltage for I/O Stages 1...4
44 IO3 I/O Stage 3
45 IO4 I/O Stage 4
46 IO5 I/O Stage 5
47 IO6 I/O Stage 6
48 VB2 Supply Voltage for I/O Stages 5...8
49 IO7 I/O Stage 7
50 IO8 I/O Stage 8
51 GNDA Ground (analog)
52 VREF External Voltage Reference (optional)
Additional Pin Function in SPI Mode
(NSP = low)
3 NCS
8 SCK
9 A1
13 SOC
28 SI
29 SOB
32 A0
33 A2
34 A4
Not Chip Select
Serial Clock
Device ID Bit 1
Serial Out Chain
Serial In
Serial Out Bus
Device ID Bit 0
Select Chain / Bus
Enable Interrupt Report SOC/SOB
Separate supply voltages at VB1..4 are possible. All GNDA pins must be connected up externally. GNDA must be
connected to GNDD externally when just one voltage supply is available. VCC and VDD can be powered either
mutually or separately.
Only the Pin 1 mark on the front or backside is determinative for package orientation (P-CODE JX and
other codes are subject to change).