IC-JX_16 Datasheet, PDF (36/48 Pages) IC-Haus GmbH – 16-FOLD 24 V HIGH-SIDE DRIVER

iC-JX
16-FOLD 24 V HIGH-SIDE DRIVER WITH µC INTERFACE
Rev C2, Page 36/48
Interrupts
Interrupt readings at NINT resp. D1/SOC or D2/SOB
can be triggered:
• by a change of (filtered) input signal
• by an overcurrent message signaled at an I/O pin
(due to a short circuit, for example)
• by undervoltage at VCC or VDD
Interrupts are deleted by setting EOI in Control Word 4
(Addr. 0x1A, P. 21). This bit then automatically resets
to 0.
NINT or SOC/SOB
signal interrupt?
yes
read Interrupt Message
Register A/B
interrupt bit
DCHI set?
yes
read Change-of-input
Register A/B to locate the
I/O stage causing the interrupt
no
• by bursts at VDD
• by the end of an A/D conversion
• by exceeding maximum temperature thresholds
(2 stages)
Interrupt outputs for each individual I/O stage can be
caused:
• by a change of input
interrupt bit
yes
ISCI set?
no
interrupt bit
yes
IEOC set?
no
any other
yes
interrupt set?
no
read Overcurrent Message A/B
to locate the I/O stage causing
the interrupt
read A/D converter data
appropriate interrupt
management
• by a short circuit (with stages in output mode)
set EOI to '1'
(Control Word 4)
The relevant interrupt enables determine which mes-
sages are stored and which are displayed (Addr.
0x10-0x13, see P. 28).
Note:
The display of interrupt messages caused by exces-
sive temperature, A/D conversion, undervoltage or
bursts is not maskable; this particular function is per-
manently enabled.
When an event occurs which is enabled to produce an
interrupt message pin NINT is set to 0. If the device is
being operated with a serial interface outputs D1/SOC
or D2/SOB are set to 1 when an interrupt occurs if no
communication is made via the interface itself and the
interrupt messaging is enabled with pin A4 (see Tab.
20, P. 42).
By reading out the Interrupt Status Register (Addr. 0x04
and 0x05, P. 29) the nature of the message can be de-
termined. In case of a change-of-input interrupt or an
overcurrent interrupt the I/O stage causing the interrupt
can be located. With a change-of-input message the
problematic I/O stage is shown in the corresponding
Change-of-input Message register (Addr. 0x02 and
0x03, P. 25); with an overcurrent interrupt the Overcur-
rent Message register (Addr. 0x06 and 0x07, P. 26)
pinpoints the I/O stage with a short circuit.
Figure 9: Interrupt management
Note:
To avoid interrupt messages caused by other sources
in the time between the readout of a interrupt status
register (Interrupt Status Register, Change-of-input
Message or Overcurrent Message) and the deletion
of the current interrupt being overlooked all interrupt
status registers are locked against further changes
and successive interrupts are stored in a pipeline. If
successive interrupts occur outputs NINT remains at
’0’ resp. D1/SOC or D2/SOB remain at ’1’ after the
present interrupt has been deleted using EOI. The
new interrupt source is displayed in the interrupt sta-
tus register and in the specific status registers.
I/O stages configured as input: logic level status
and Change-of-input Message
Any change to an input signal IOx is accepted via digital
filtering only after the selected filter time has expired.
The scaling factor for the filter times and the input filter
bypass can be programmed separately for all four nib-
bles (see Control Word 1, Addr. 0x14 and 0x15, P. 16).
The clock source for all filters can be programmed with
SECLK (see Control Word 3B, Addr. 0x19, P. 20).
Input Registers A/B (Addr. 0x00 and 0x01, P. 25) repre-
sent the actual status of the I/O stages. A high at IOx