IC-JX_16 Datasheet, PDF (20/48 Pages) IC-Haus GmbH – 16-FOLD 24 V HIGH-SIDE DRIVER

iC-JX
16-FOLD 24 V HIGH-SIDE DRIVER WITH µC INTERFACE
Control Word 3: flash pulse and reference clock
Rev C2, Page 20/48
Control Word 3A (flash pulse settings)
Bit
Name
Nibble 3:
I/O-Pins 13..16
7
6
PN31
PN30
Nibble 2:
I/O-Pins 9..12
5
4
PN21
PN20
Nibble 1:
I/O-Pins 5..8
3
2
PN11
PN10
Addr.
0x18
Reset-state : 0x00
Nibble 0:
I/O-Pins 1..4
1
0
PN01
PN00
Control Word 3A: Nibble 0-3
Nibble3, Bit7..6
PN31
PN30
Flash frequency
Flash frequency
Nibble2, Bit5..4
PN21
PN20
Nibble1, Bit3..2
PN11
PN10
Nibble0, Bit1..0
PN01
PN00
SEBLQ¹ = 0
SEBLQ¹ = 1
0
0
f(BLFQ)
f(SECLK)/2¹⁹ ≈ 2.38 Hz^a
(r)
0
1
f(BLFQ)/2
f(SECLK)/2²⁰ ≈ 1.19 Hz^a
1
0
f(BLFQ)/4
f(SECLK)/2²¹ ≈ 596 mHz^a
1
1
f(BLFQ)/16
f(SECLK)/2²³ ≈ 149 mHz^a
1 _{SEBLQ: see Control Word 3B}
a _{Flash frequency derived from system clock configured with f(SECLK}1_{) @ 1.25MHz}
Control Word 3B (reference clock)
Addr. 0x19
reset entry: 0x00
Bit
7
6
5
4
3
2
1
0
Name
-
-
-
-
SECLK1 SECLK0 -
SEBLQ
Bit0
SEBLQ Settings for flash frequency
SEBLQ 0
The flashing pulse is derived from the external clock signal at BLFQ
(r)
1
The flashing pulse is derived from the system clock SECLK
Bit3..2
SECLK1
SECLK1..0 0
0
1
1
SECLK0
0
1
0
1
Settings for system clock SECLK
Operation with the clock signal at CLK
(r)
Operation with the internal clock signal ICLK (see Elec. Charac. 713)
Operation without the clock signal at CLK (filtering etc. deactivated)
reserved