IC-JX_16 Datasheet, PDF (41/48 Pages) IC-Haus GmbH – 16-FOLD 24 V HIGH-SIDE DRIVER

iC-JX
16-FOLD 24 V HIGH-SIDE DRIVER WITH µC INTERFACE
Rev C2, Page 41/48
SPI modes 0 and 3 are supported, i.e. idle level of
SCK 0 or 1, acceptance of data on a rising edge. In
order to ensure communication between the iC-JX and
standard micro controllers, address and data words are
both eight bit wide. Data is sent MSB first. The pins
used for SPI communication are summarized in Tab.
18.
Pins used in SPI mode
Pin
Function
A3/SCK clock input
NCS
chip select input
D0/SI
D1/SOC
D2/SOB
data input
data output chain¹
data output bus¹
Note
1 _{see Tab. 19}
The configuration (bus or chain) is set using pin A2. If
A2 is at 0, the devices are in chain operation; if A2 is at
’1’, the chips switch to bus configuration.
SPI configuration (bus or chain)
Pin A2
selected configuration
0
chain
1
bus
data output
SOC
SOB
Table 19: Selection of bus or chain SPI configuration
with pin A2
Several iC-JXs can be operated on an SPI (see Fig. 14;
SPI daisy chain: max. 4; SPI Bus with shared NCS:
max. 4; SPI Bus with individual slaves: no limitation).
Table 18: Pins used in SPI Mode (NSP = 0)
SPI-daisy chain (pin A2=0)
00
SI
iC-JX
A0 A1
SOC
NCS SCK SOB
01
SI
iC-JX
A0 A1
SOC
NCS SCK SOB
10
SI
iC-JX
A0 A1
SOC
NCS SCK SOB
11
SI
iC-JX
A0 A1
SOC
NCS SCK SOB
MOSI
NCS
SCK
MISO
SPI-bus with shared NCS (pin A2=1) _{0 0}
SI
iC-JX
A0 A1
SOC
NCS SCK SOB
01
SI
iC-JX
A0 A1
SOC
NCS SCK SOB
10
SI
iC-JX
A0 A1
SOC
NCS SCK SOB
11
SI
iC-JX
A0 A1
SOC
NCS SCK SOB
MOSI
NCS
SCK
MISO
SPI-bus with individual slaves (pin A2=1)
00
SI
iC-JX
A0 A1
SOC
NCS SCK SOB
00
SI
iC-JX
A0 A1
SOC
...
NCS SCK SOB
00
SI
iC-JX
A0 A1
SOC
NCS SCK SOB
MOSI
NCS 1
NCS 2
NCS n
SCK
MISO
Figure 14: Possible SPI configurations (pin NSP=0)
In chain configuration (see Figure 14, top) output SOC following chip; output SOB is not used. During the ad-
of a device is connected up to the SI data input of the