IC-JX_16 Datasheet, PDF (44/48 Pages) IC-Haus GmbH – 16-FOLD 24 V HIGH-SIDE DRIVER

iC-JX
16-FOLD 24 V HIGH-SIDE DRIVER WITH µC INTERFACE
Rev C2, Page 44/48
The master recognizes a correct transmission by the
fact that the control byte was received without error.
Control Byte
0x59
other values
Status of transmission
correct transmission
error during transmission
NoB
0x0F
0x1E
0x2D
0x3C
0x4B
0x5A
0x69
0x78
Number of bytes
1
2
3
4
5
6
7
8
NoB
0x87
0x96
0xA5
0xB4
0xC3
0xD2
0xE1
0xF0
Number of bytes
9
10
11
12
13
14
15
16
Table 21: Status of transmission indicated by Control Table 22: Setting the number of bytes to send/receive
Byte
with NoB
SPI: Reading multiple data from an iC-JX
NCS
D0/SI
StartAdr
NoB
D1/SOC
D2/SOB
StartAdr
-transparent-
Figure 18: SPI: Reading several values of consecutive register addresses (auto-increment)
If data from several consecutive registers is to be read
out (see Figure 18), the auto-increment function en-
ables an abbreviated transmission protocol to be run
using iC-JX. As in the reading of a single byte the con-
troller sends the address, a NOP byte and the NoB byte
(Number of bytes ≥ 2, see Tab. 22).
The addressed iC-JX repeats the start address and
then transmits the consecutive register values and af-
ter one byte checks the data returned from the master
for errors. Once the required number of register val-
ues has been sent the slave transmits the address of
the last register addressed (EndAdr), followed by the
control byte 0x59 with error-free transmission or the
inverted value 0xA6 with an error in transmission. Dur-
ing transmission of the control byte the synchronism
of the signals at SI and SOC/SOB is again checked; if
these are not synchronous, on recognition of this fact
the slave then transmits the inverted control byte.