IC-JX_16 Datasheet, PDF (12/48 Pages) IC-Haus GmbH – 16-FOLD 24 V HIGH-SIDE DRIVER

iC-JX
16-FOLD 24 V HIGH-SIDE DRIVER WITH µC INTERFACE
OPERATING REQUIREMENTS: Parallel µC Interface
Operating Conditions: VCC = VDD = 3...5.5 V, VBy = 12...36 V, GNDA = GNDD = 0 V, RSET = 10 kΩ ±1 %
Ta = 0...70 °C, CL() = 150 pF, input level lo = 0.8 V, hi = 2.2 V, reference levels according to figure 3
Item Symbol Parameter
No.
Conditions
Read Cycle
I001 t_AR1, t_AR2 Setup Time:
see Figure 4
NCS, A0...4 set before NRD hi → lo
I002 t_RA
Hold Time: NCS, A0...4 set before NRD see Figure 4
lo → hi
I003 t_RD
Wait Time : Data valid after NRD hi → see Figure 4
lo
I004 t_DF
Hold Time: Data Bus high impedance see Figure 4
after NRD lo → hi
I005 t_RL
Write Cycle
Required Read Signal Duration at NRD
I006 t_AW1, t_AW2 Setup Time: NCS, A0...4 set before
NWR lo → hi
see Figure 4
I007 t_DW
Setup time :
Data valid before NWR lo → hi
see Figure 4
I008 t_WA
Hold time:
see Figure 4
NCS, A0...4 stable after NWR lo → hi
I009 t_WD
Hold time:
Data valid after NWR lo → hi
see Figure 4
I010 t_WL
Required Write Signal Duration at NWR see Figure 4
Read/Write Timing
I011 tcyc
Recovery Time between cycles:
NRD lo → hi to NRD hi → lo,
NRD lo → hi to NWR hi → lo,
NWR lo → hi to NWR hi → lo,
NWR lo → hi to NRD hi → lo
see Figure 4
Rev C2, Page 12/48
Min.
30
0
50
30
100
10
10
50
165
Unit
Max.
ns
ns
120
ns
65
ns
ns
ns
ns
ns
ns
ns
ns
t _cyc
A(4:0)
V
2.4V
2.0V
Input/Output
0.8V
0.45V
1
t
0
Figure 3: Reference levels for displayed
values of time
NCS
t _RA
t_WA
NRD
NWR
D(7:0)
t _AR1
t _AR2
t _DF
valid
t_RD
t _RL
t _AW1
t _AW2
t _WD
valid
t _DW
t _WL
Figure 4: Read and write cycle for the parallel interface