IC-JX_16 Datasheet, PDF (32/48 Pages) IC-Haus GmbH – 16-FOLD 24 V HIGH-SIDE DRIVER

iC-JX
16-FOLD 24 V HIGH-SIDE DRIVER WITH µC INTERFACE
Rev C2, Page 32/48
Note:
If the temperature rises above Toff2 the pull-up/down
current sources are shut down and are reactivated
only if the temperature falls below Ton2 (see P. 37).
Enable outputs
The I/O stages configured as output (Control Word 2
(Addr. 0x16 and 0x17, P. 18) can be enabled individ-
ually with Output-Register A/B (Addr. 0x0C, 0x0D, P.
24).
Notes:
The corresponding output has to be enabled in the
Output Register (Addr. 0x0C, 0x0D, P. 24) for the
flash function to be visible at the output.
If the temperature rises above Toff2 the Flash Pulse
Enable A/B registers are reset (see P. 37).
Pin RSET
To set the reference current needed by iC-JX an exter-
nal resistor of 10 kΩ must be connected from RSET to
ground.
Notes:
Pin POE can disable all output stages (see Tab. 8, P.
32).
If the temperature rises above Toff2 the Output-Regis-
ters A/B are reset to disable the output transistors of
the I/O stages and thus to minimize power dissipation
(see P. 37).
External reset
A reset (NRES = 0) sets the register entries to the re-
set values given in the tables (see chapter REGISTER
DETAILS).
Device identification
An identification code has been introduced to enable
identification of iC-JX.
Forced shutdown of output stages
All output stages can be forcibly shut down at input
POE (see Tab. 8). This function allows a processor-in-
dependent watchdog to lock the outputs in the event
of error, for example. An integrated pull-down resistor
increases safety.
Forced shutdown of output stages
Pin POE output stages
0
disabled
1
enabled (according to Output Register A/B)
Table 8: Forced shutdown of output stages with pin
POE
Flash pulse settings
The output stages can be individually set to flash mode
with the registers Flash Pulse Enable A/B (Addr. 0x0E,
0x0F, P. 24). The blink or flash frequency can be de-
rived from pin BLFQ or from system clock (SEBLQ:
Control Word 3B, Addr. 0x19, P. 20). Note that also the
system clock can be applied externally to pin CLK or be
generated internally (SECLK: Control Word 3B, Addr.
0x19, P. 20). Different flash frequencies can be set for
all four nibbles (Control Word 3A, Addr. 0x18, P.20).
DID(4:0)
Code
0x15
Addr. 0x1D; bit 4:0
Device ID
iC-JX
Table 9: Device ID iC-JX
Operation without the external CLK signal
iC-JX can be operated without an external clock at pin
CLK. Using Control Word 3B (Addr. 0x19, P. 20) the
device can be set to an internally generated clock fre-
quency; In this instance all filter functions remain fully
available.
Via SECLK in Control Word 3B the clocked filtering for
the I/O signals and overcurrent messaging can also
be deactivated. The same behavior can be obtained
by setting BYP0, BYP1, BYP2 and BYP3 in Control
Word 1 (Addr. 0x14 and 0x15, see P. 16) together with
BYPSCF in Control Word 4 (Addr. 0x1A, see P. 21); all
filters are avoided by way of a bypass circuit.
Note:
When the filtering of the I/O messages and the
overcurrent messages is deactivated with SECLK or
BYPO..3 interferences in the line can lead to the un-
wanted display of interrupts.