IC-JX_16 Datasheet, PDF (42/48 Pages) IC-Haus GmbH – 16-FOLD 24 V HIGH-SIDE DRIVER

iC-JX
16-FOLD 24 V HIGH-SIDE DRIVER WITH µC INTERFACE
Rev C2, Page 42/48
dressing sequence (1 byte of communication) all iC-JXs
are switched through transparently so that all devices
receive the transmitted address simultaneously. Only
the addressed chip then goes into data transfer mode;
the others remain transparent so that communication
between the controller and addressed iC-JX can take
place without delay. It must be noted here that even
in transparent mode each iC-JX has a certain transmit
time which has an effect on the maximum data fre-
quency of the overall system. The advantage of this
configuration lies in the fact that it is possible to read
out the values of an address in all devices very quickly.
In bus configuration (see Figure 14, center ) all SI in-
puts and SOB outputs are switched in parallel; the SOC
outputs are not used. Addressing the devices ensures
that only one of the chips outputs data to SOB; the
outputs of the inactive iCs are switched to tristate. This
type of configuration differs from chain configuration in
that it permits higher clock rates and also allows up to
four iC-JXs to be connected up to an SPI bus.
If no communication takes place on the SPI the chips
can send interrupts to the controller by switching the
master MISO line to 1. To this end all iC-JXs in chain
configuration are switched through transparently (see
Figure 15). In case of an interrupt message SOC is set
to 1. In bus configuration the relevant chip drives a 1 at
its SOB output towards the pull-down resistors at the
outputs of the other devices.
Using pin A4 settings can be made as to whether inter-
rupts are signaled to the master via the SOB or SOC
pin (see Tab. 20).
Note:
The interrupt messaging via SOB must be deactivated
in bus configuration if further non iC-JX devices are
present on the SPI bus as otherwise data can collide
on the bus which is not desirable here.
Interrupt Messaging via SOB/SOC
Pin A4
interrupt message to pin SOB/SOC
0
1
Note
disabled
enabled ^*)
*) _{SOB/SOC = 1 in case of an interrupt}
Table 20: Interrupt Messaging via SOB/SOC configura-
tion with pin A4
3..5.5V
0V
VDD
GND
MISO
SCK
NCS
MOSI
Address
SEL Comparator
JX-Logic
NINT
D0/SI
Evaluation NERR
Shift register
A3/SCK NCS
JX0
D1/
SOC
&
Address
SEL Comparator
JX-Logic
NINT
D0/SI
Evaluation NERR
Shift register
A3/SCK NCS
JX1
D1/
SOC
&
Address
SEL Comparator
JX-Logic
NINT
D0/SI
Evaluation NERR
Shift register
A3/SCK NCS
JX2
D1/
SOC
&
Address
SEL Comparator
JX-Logic
NINT
D0/SI
Evaluation NERR
Shift register
A3/SCK NCS
JX3
D1/
SOC
&
Figure 15: Addressing and interrupt messaging scheme in chain configuration