GMS81C50 Datasheet, PDF (98/99 Pages) Hynix Semiconductor – 8-BIT SINGLE CHIP MICROCONTROLLERS

Appendix B. Programmer’s guide
2. Mask Option List Example Refer to Circuit B-1
GMS81C50 MASK OPTION LIST
Code Name : GMS81C5016 - Uxxx
1. Device & Package
LG Semicon Co., Ltd.
M/L Application Team.
GMS81C5004
GMS81C5008
GMS81C5016
28PIN : SOP
40PIN : PDIP
44PIN : PLCC
GMS81C5024
GMS81C5032
28 PIN : Skinny DIP
44PIN : MQFP
- R0 PORT
Y : Yes N : No
Port
R00 R01 R02 R03 R04 R05 R06 R07
Y/N
yyyyy y yy
Y/N*3
yyyyy y yy
- R1 PORT
Y : Yes N : No
Port
Y/N
Y/N*3
R10 R11 R12 R13 R14 R15 R16 R17
yyyyy y yy
yyyyy y yy
- R2 PORT
Y : Yes N : No
Port
Y/N
Y/N*3
R20 R21 R22 R23 R24 R25 *2 R26 *2 R27 *2
yyyyy y yy
yyyyy y yy
- R3 PORT
Y : Yes N : No
Port
Y/N
Y/N*3
R30 *2 R31 *2 R32 *2 R33 *2 R34 *2 R35 *2 R36 *2 R37 *2
yyyyy y yy
yyyyy y yy
- R4 PORT
Y : Yes N : No
Port
Y/N
Y/N*3
R40 *2
y
y
< NOTICE >
. *1 : is not available for 28PIN & 40PIN. So, Default option is Pull-Up.
. *2 : is not available for 28PIN. So, Default Option is Pull-Up.
. *3 : is for selecting Pull-up in LVD mode.
3. Low Voltage Detection
(Means RAM retention)
Y/N
Y
Date
:
Company Name :
Section Name :
Signature
:
Note: Caution: When the power to the MCU would be de-
creased under LVD, all I/O ports are changed to input ports
with pull up resistor. In below cases, you must take care of
selecting the pull up in LVD.. You must detach the pull up
of I/O port at thease cases.
Case1 : When any I/O port is connected to GND, the cur-
rent will flow from the Pull up to GND. It cause the large
power consumption and RAM would not be retained
enough to satisfy your want.
Case2 : The case of using any I/O port for controlling PNP
TR., The TR is always turn on by the Pull up of I/O port in
LVD mode
R00
< Case 1 >
R00
PNP
< Case 2 >
B-3