GMS81C50 Datasheet, PDF (63/99 Pages) Hynix Semiconductor – 8-BIT SINGLE CHIP MICROCONTROLLERS

GMS81C50 Series
(2) Interrupt Timing
HYUNDAI
CLOCK
SYNC
A command before interrupt
interrupt process step
Interrupt Request Sampling
Figure 12-2 Interrupt Enable Accept Timing
*Interrupt Request sampling time
-Maximum 12 machine cycle (When execute DIV
instruction)
-Minimum 0 machine cycle
*Interrupt preprocess step is 8 machine cycle
*Interrupt overhead
-Maximum 1 + 12 + 8 = 21 machine cycle
-Minimum 1 + 0 + 8 = 9 machine cycle
(3) The valid timing after executing Interrupt control instructions
I flag is valid just after executing of EI/DI on the contrary.
Interrupt Enable register is valid one instruction after con-
trolling interrupt Enable Register.
12.4 INTERRUPT PROCESSING SEQUENCE
When an interrupt is accepted, the on-going process is
stopped and the interrupt service routine is executed. After
the interrupt service routine is completed it is necessary to
restore everything to the state before the interrupt oc-
cured.As soon as an interrupt is accepted, the content of the
program counter and PSW are savedin the stack area. At
the same time, the content of the vector address corre-
sponding to the accepted interrupt, which is in the interrupt
vector table, enters into the program counter and interrupt
service is executed. In order to execute the interrupt ser-
vice routine, it is necessary to write the jump addresses in
the vector table (FFE0 h ~ FFFF h) corresponding to each
interrupt
* Interrupt Processing Step
1) Store upper byte of Program Counter, SP <= SP
2) Store lower byte of Program Counter, SP <= SP - 1
3) Store Program Status Word, SP <= SP - 2
4) After resetting of I-flag, clear accepted Interrupt Re-
quest Flag. (Set B-flag for BRK Instruction)
5) Call Interrupt service routine
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