GMS81C50 Datasheet, PDF (47/99 Pages) Hynix Semiconductor – 8-BIT SINGLE CHIP MICROCONTROLLERS

GMS81C50 Series
HYUNDAI
ister is written, then CKCTLR register with same address
is written.
7
Basic Interval Timer Register
0
BITR
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
R <00C7 h>
11.2 Timer0, Timer1, Timer2
(1) Timer Operation Mode
Timer consists of 16bit binary counter Timer0 (T0), 8bit
binary Timer1 (T1), Timer2 (T2), Timer Data Register,
Timer Mode Register (TM01, TM0, TM1, TM2) and con-
trol circuit. Timer Data Register Consists of Timer0 High-
MSB Data Register (T0HMD), Timer0 High-LSB Data
Register (T0HLD), Timer0 Low-MSB Data Register
(T0LMD), Timer0 Low-LSB Data Register (T0LLD),
Timer1 High Data Register (T1HD), Timer1 Low Data
Register (T1LD), Timer2 Data Register (T2DR). Any of
the PS0 ~ PS5, PS11 and external event input EC can be
selected as clock source for T0. Any of the PS0 ~ PS3, PS7
~ PS10 can be selected as clock T1. Any of the PS5 ~ PS12
can be selected as clock source for T2.
* Relevant Port Mode Register (PMR1 : 00C9 h) value
should be assigned for event counter,
Timer0
- 16-bit Interval Timer
- 16-bit Event Counter
- 16-bit Input Capture
- 16-bit rectangular-wave output
Timer1
- 8-bit Interval Timer
- 8-bit rectangular-wave output
- 8-bit Interval Timer
Timer2 - 8-bit rectangular-wave output
- Modulo-N Mode
- Single/Modulo-N Mode
- Timer Output Initial Value Setting
- Timer0~Timer1 combination Logic Output
- One Interrupt Generating Every 2nd
Counter Overflow
44