GMS81C50 Datasheet, PDF (61/99 Pages) Hynix Semiconductor – 8-BIT SINGLE CHIP MICROCONTROLLERS

GMS81C50 Series
HYUNDAI
Mask
non-maskable
Hardwar
e
Interrupt
maskable
Priority
-
0
1
2
3
4
5
6
7
Interrupt Source
INT Vector High
RST (RESET pin)
FFFF
KSCNR (Key Scan)
FFFB
INT1R (External Interrupt1)
FFF9
INT2R (External Interrupt2)
FFF7
T0R (Timer0)
FFF3
T1R (Timer1)
FFF1
T2R (Timer2)
FFEF
WDTR (Watctdog Timer)
FFE9
BITR (Basic Interval Timer)
FFE7
INT Vector Low
FFFE
FFFA
FFF8
FFF6
FFF2
FFF0
FFEE
FFE8
FFE6
-
-
BRK instruction
FFDF
FFDE
Table 12-1 Interrupt Priority & Source
12.2 INTERRUPT CONTROL REGISTER
I flag of PSW is a interrupt mask enable flag. When I flag
= ``0``, all interrupts become disable. When I flag = ``1``,
interrupts can be selectively enabled and disabled by con-
tents of corresponding Interrupt Enable Register. When in-
terrupt is occured, interrupt request flag is set, and
Interrupt request is detected at the edge of interrupt signal.
The accepted interrupt request flag is automatically cleared
during interrupt cycle process. The interrupt request flag
maintains ``1`` until the interrupt is accepted or is cleared
in program. In reset state, interrupt request flag register
(IRQH, IRQL) is cleared to ``0``. It is possible to read the
state of interrupt register and to mainpulate the contents of
register and to generate interrupt. (Refer to software inter-
rupt).
IENL
-
WDTR BITE
-
IENH
KSCNE INT1E INT2E
-
IRQL
-
WDTR BITE
-
IRQH
KSCNE INT1R INT2R
-
-
-
-
T0E
T1E
T2E
-
-
-
T0R
T1R
T2R
IENL : INTERRUPT ENABLE REGISTER LOW
IENH : INTERRUPT ENABLE REGISTER HIGH
IRQL : INTERRUPT REQUEST REGISTER LOW
IRQH : INTERRUPT REQUEST REGISTER HIGH
R/W <00CCh>
-
R/W <00CEh>
-
R/W <00CDh>
-
R/W <00CFh>
-
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