GMS81C50 Datasheet, PDF (64/99 Pages) Hynix Semiconductor – 8-BIT SINGLE CHIP MICROCONTROLLERS

HYUNDAI
GMS81C50 Series
clock
SYNC
R/W
internal
addr bus
internal
data bus
internal
READ
internal
WRITE
Interrupt Process Step
ISR
*1
*2 *3
PC
SP SP-1
SP-2
LVA HVA new PC
=====
OP OP PCH PCL PSW
CODE CODE
==
``L`` ``H``
vector vector
*1 ISR
*2 LVA
*3 HVA
: Interrupt Service
Routine
: Low Vector Address
: High Vector Address
Figure 12-3 Interrupt Procesing Step Timing
12.5 SOFTWARE INTERRUPT (Interrupt by Break (BRK) Instruction)
Software interrupt is available just by writing
``Break(BRK)`` instruction. The values of PC and PSW is
stacked by BRK instruction and then B flag of PSW is set
and I flag is reset.
Flag change by BRK execution
PSW
N
V
G
B
H
I
Z
C
set
reset
PSW
N
V
G
1
H
0
Z
C
(Right after BRK execution)
Interrupt vector of BRK instruction is shared by vector of
Table Call (TCALL0). When both instruction of BRK and
TCALL0 are used, as shown in Figure 12-4 each process-
ing routine is judged by contents of B flag. There is no in-
struction to reset directly B flag.
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