GMS81C50 Datasheet, PDF (70/99 Pages) Hynix Semiconductor – 8-BIT SINGLE CHIP MICROCONTROLLERS

HYUNDAI
GMS81C50 Series
WDTR
7
Watch DOG Timer Register
0
-
WDTCL WDTR5 WDTR4 WDTR3 WDTR2 WDTR1 WDTR0 W <00C8 h>
Determine Interval of IFWDT
Interval of IFWDT = Value of WDTR > Interval of IFBIT
WDTCL
0
1
Watch Dog Timer Operation
free-run
Automatically cleared, after one machine cycle
13.2 WDT Interrupt Interval
WDT Interrupt (IFWDT) interval is determined by the in-
terrupt IFBIT interval of Basic Interval Timer and the val-
ue of WDT Register.
-Interval of IFWDT = (IFBIT interval) * (WDTR value)
-Interval of IFWDT : 512 us * 1 = 512 us (MIN>)
-65,536us * 63 = 4,128,768 us (MAX>)
As IFBIT (Basic Interval Timer Interrupt Request) is used
for input clock of WDT, Input clock cycle is possible from
512 us to 65,536 us by BTS. (at fex = 4MHz)
*At Hardware reset time ,WDT starts automatically.
Therefore, the user must select the CKCTLR, WDTR be-
fore WDT overflow.
-Reset WDTR value = 0F h,15
-interval of WDT = 65,536 * 15 = 983040 us
(about 1second )
67