GMS81C50 Datasheet, PDF (62/99 Pages) Hynix Semiconductor – 8-BIT SINGLE CHIP MICROCONTROLLERS

HYUNDAI
GMS81C50 Series
12.3 INTERRUPT ACCEPT MODE
The interrupt priority order is determined by bit (IM1,
IM0) of IMOD register.
7
IMOD
-
Interrupt Mode Register
0
-
IM1
IM0
IP3
IP2
IP1
IP0
R/W <00CA h>
Assigning by interrupt accept mode bit
IM1
IM0
Priority
0
0
fixed by hardware
0
1
changeable by IP3~ IP0
1
*
Interrupt is inhibited
(1) Selection of Interrupt by IP3-IP0
The condition allow for accepting interrupt is set state of
the interrupt mask enable flag and
the interrupt enable bit must be ``1``. In Reset state, these
IP3 - IP0 registers become all ``0``.
IP3
IP2
IP1
IP0
Selection Interrupt
0
0
0
1
KSCNR (Key Scan)
0
0
1
0
INT1R (External interrupt 1)
0
0
1
1
INT2R (External interrupt 2)
0
1
0
0
Reserved
0
1
0
1
T0R (Timer 0)
0
1
1
0
T1R (Timer 1)
0
1
1
1
T2R (Timer 2)
1
0
0
0
Reserved
1
0
0
1
Reserved
1
0
1
0
WDTR (Watch Dog Timer)
1
0
1
1
BITR (Basic Interval Timer)
1
1
0
0
Reserved
Table 12-2 Interrupt Selection by IP3 - IP0
59