GMS81C50 Datasheet, PDF (45/99 Pages) Hynix Semiconductor – 8-BIT SINGLE CHIP MICROCONTROLLERS

GMS81C50 Series
HYUNDAI
11. TIMER
11.1 Basic Interval Timer
The GMS81C50 Series has one 8-bit Basic Interval Timer
that is free-run and can not stop. Block diagram is shown
in Figure 11-1 .
The Basic Interval Timer generates the time base for key
scanning, watchdog timer counting, and etc. It also pro-
vides a Basic interval timer interrupt (IFBIT). As the count
overflow from FF_H to 00_H, this overflow causes the inter-
rupt to be generated.
-8bit binary counter
-Use the bit output of prescaler as input to secure the oscil-
lation stabilization time after power-on
-Secures the oscillation stabilization time in standby mode
(stop mode) release
-Contents of B.I.T can be read
-Provides the clock for watch dog timer.
DATA BUS
-
-
WDTON ENPCK BTCL
BTS2
BTS1
BTS0 CKCTLR
PS3
PS4
PS5
PS6
PS7
PS8
PS9
PS10
MUX
BIT0
BIT1
BIT2
BIT3
BIT4
BIT5
BIT6
BITR
BIT7
IFBIT
DATA BUS
Figure 11-1 Block Diagram of Basic Interval Timer
(1) Control of B.I.T
The Basic Interval Timer is controlled by the clock control
register (CKCTLR) shown in Figure 11-2 . If bit3(BTCL)
of CKCTLR is set to ``1``, B.I.T is cleared, and then, after
one machine cycle, BTCL becomes ``0``, and B.I.T starts
counting. BTCL is set to ``0`` in reset state.
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