GMS81C50 Datasheet, PDF (65/99 Pages) Hynix Semiconductor – 8-BIT SINGLE CHIP MICROCONTROLLERS

GMS81C50 Series
HYUNDAI
BRK or
TCALL0
B flag
0
1
BRK INTERRUPT ROUTINE
TCALL0 ROUTINE
RETI
RET
Figure 12-4 Execution of BRK or TCALL0
12.6 MULTIPLE INTERRUPT
If there is an interrupt, Interrupt Mask Enable Flag is auto-
matically cleared before entering the Interrupt Service
Routine. After then, no interrupt is accepted. If EI instruc-
tion is executed, interrupt mask enable bit becomes ``1``,
and each enable bit can accept interrupt request. When two
or more interrupts are generated simultaneously, the high-
est priority interrupt set by Interrupt Mode Register is ac-
cepted.
12.7 Key Scan Input Processing
(1) Standby Mode Release Register (SMRR)
Key Scan Interrupt is generated by detecting low or high
Input from each Input pin (R0, R1) is one of the sources
which release standby (SLEEP, STOP) mode. Key Scan
ports are all 16bit which are controlled by Standby Mode
Release Register (SMRR0, SMRR1). Key Input is consid-
ered as Interrupt, therefore, KSCNE bit of IEHN should be
set for correct interrupt executing, SLEEP mode and STOP
mode, the rest of executing is the same as that of external
Interrupt. Each SMRR Register bit is allowed for each port
(for Bit= ``0``, no Key Input, for Bit= ``1``, Key Input
available). At reset, SMRR becomes ``00 h``. So, there is
no Key Input source.
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