GMS81C50 Datasheet, PDF (60/99 Pages) Hynix Semiconductor – 8-BIT SINGLE CHIP MICROCONTROLLERS

HYUNDAI
GMS81C50 Series
12. INTERRUPTS
The GMS81C50 Series interrupt circuits consist of Inter-
rupt Mode Register (MOD), Interrupt enable register
(IENH, IENL), Interrupt request flags of IRQH, IRQL,
Priority circuit and Master enable flag ("I" flag of PSW). 8
interrupt sources are provided. The configuration of inter-
rupt circuit is shown in Figure 12-1 .
The GMS81C50 Series contains 8 interrupt sources; 3 ex-
ternals and 5 internals. Nested interrupt services with pri-
ority control is also possible. Software interrupt is non-
maskable interrupt, the others are all maskable interrupts.
- 8 interrupt source (2Ext, 3Timer, BIT, WDT and Key
Scan)
- 8 interrupt vector
- Nested interrupt control is possible
- Programmable interrupt mode
- Hardware accept mode
- Software selection accept mode
- Read and write of interrupt request flag are possible.
- In interrupt accept, request flag is automatically cleared.
0
IENL
-----
Internal Data Bus
7
0
-
-
IENH
-
7
0
IMOD
7
--
KSCN KSCNR
INT1 INT1R
INT2 INT2R
IFT0 T0R
IFT1 T1R
IFT2 T2R
IFWDT WDTR
IFBIT
BITR
IRQ
PRIORITY
CONTROL
INT.
VECTOR
ADDR.
Figure 12-1 Block Diagram of Interrupt
BRK
Standby Mode Release
12.1 Interrupt priority and sources.
Each interrupt vector is independent and has its own prior-
ity. Software interrupt (BRK) is also available. Interrupt
source classification is shown in Table 12-1.
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