GMS84512 Datasheet, PDF (82/123 Pages) Hynix Semiconductor – 8-BIT SINGLE CHIP MICROCOMPUTER

GMS 84512 / 84524
l The vlaid timing after executing Interrupt control Flag
¨Í I-Flag is valid, after EI, DI executed
¨Î IENH, IENL register is valid after next instruction
4.1.3 INTERRUPT SEQUENCE
When interrupt is accepted, the execution program is stopped, a certain of
interrupt processing step is passed, and interrupt sevice routine is started.
By last instruction of interrupt service routine(RETI) return to original program.
l Interrupt Process Sequence
PCH Stacking
sp¡çsp -1
PCL Stacking
sp¡çsp -1
PSW Stacking
sp¡çsp -1
I-Flag = “0”
(B-Flag= “1” at BRK)
Interrupt Service
Routine
System Clock
Instruction
Fetch
Address Bus
Data Bus
Internal Read
Internal Write
pc
sp sp-1
sp-2
V.L V.H new pc
not Used PCH PCL PSW V.L ADL ADH Opcode
Interrupt Process Step
Interrupt Service Routine
V.L, V.H is Vector Address, ADL, ADH is start Address of Interrupt Service
Routine as Vector Contents
FIG. 4.1.3 Interrupt Process Step Timing
4-6