GMS84512 Datasheet, PDF (48/123 Pages) Hynix Semiconductor – 8-BIT SINGLE CHIP MICROCOMPUTER

GMS 84512 / 84524
l Any of the PS2, PS4, PS6 or PS8 can be selected as the clock source of T0 by bit1(T0SLI)
and bit0(T0SL0) of TM0. Andy of the PS2, PS4, PS6 or overflow of T0 can be selected as
the clock source of T1 by bit5(T1SL1) and bit4(T1SL0) of TM0.
l The operation of T0, T1 is controlled by bit3(T0ST), bit2(T0CN) and bit6(T1ST) of TM0. T0CN
controls count stop/start without clearing counter. T0ST and T1ST control count stop/start.
In order to enable timer to count-up, T0CN, T0ST and T1St should become “1”. After clearing
T0, T1 in order to count-up. T0st or T1ST should become “0” for a moment and return to “1”.
TDR0 VALUE
MATCH
MATCH
T0 VALUE
00_H
Clear
Clear
Clear
IFT0
T0ST
T0CN
COUNTER
Interrupt
Interrupt
“0”
“1” Clear & Start
“0” “1” Start
Count
Stop
Count Stop
Count
FIG 3.3.4 START/ STOP Control of Timer0
l The 16-bit interval timer is selected by assigning bit5(T1SL1) and bit4(T1SL0) to “0”.)
At 16-bit timer mode, IFT0 interrupt only is valid. It is prefered to write to the TDR in
non counting timer in order to protect undesirable interrupt.
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