GMS84512 Datasheet, PDF (79/123 Pages) Hynix Semiconductor – 8-BIT SINGLE CHIP MICROCOMPUTER

GMS 84512 / 84524
TABLE 4.1.1 Interrupt Request Source
Type
Mask Priority
Interrupt Request Source
Non
Maskable
Hardware
Interrupt
Mask
Enable
S/W Interrupt Non
Maskable
1 RST Reset Pin
2 OSD On Screen Display
3 INT1R External Interrupt 1
4 INT2R External Interrupt 2
5 T0R Timer 0
6 T2R Timer 2
7 _{1ms 1§Â Interrupt}
8 VSYNC V-sync Interrupt
9 T1R Timer 1
10 T3R Timer 3
11 INT3R External Interrupt 3
12 WDTR Watch Dog Timer
13 BITR Basic Interval Timer
14 SR
Serial I/O
¡ª ^{BRK Break Instruction}
Vector
H
FFFF_H
Vector
L
FFFE_H
FFFB_H
FFF9_H
FFF7_H
FFF5_H
FFF3_H
FFF1_H
FFEF_H
FFED_H
FFEB_H
FFE9_H
FFE7_H
FFE5_H
FFE3_H
FFDF_H
FFFA_H
FFF8_H
FFF6_H
FFF4_H
FFF2_H
FFF0_H
FFEE_H
FFEC_H
FFEA_H
FFE8_H
FFE6_H
FFE4_H
FFE2_H
FFDE_H
4.1.2 Interrupt Control
l To process interrupt, set the interrupt master enable flag I-Flag(3'rd bit of PSW). when
I-Flag="0" all interrupts are disable except RESET and S/W interrupt.
l Interrupt Enable Register ( IENH, IENL) includes interrupt enable bits of each interrupt `
source, and interrupt is accepted when the interrupt enable bit and the interrupt request bit
are both "1".
INTERRUPT ENABLE REGISTER H, L
IENH
<00EA_H>
R/W
7
R/W
6
R/W
5
R/W
4
R/W
3
R/W
2
R/W
1
R/W
0
OSDE INT1E INT2E T0E T2E 1mE Vsync T1E
E
IENL
<00E8_H>
R/W R/W R/W R/W R/W ¦¡
¦¡
¦¡
7
6
5
4
3
2
1
0
T3E INT3E WDTE BITE SE ¦¡
¦¡
¦¡
Interrupt Masking Flag
0 : Interrupt Disable
1 : Interrupt Enable
Initial Value (At Reset)
[ 0000 0000 ]
Initial Value (At Reset)
[ 0000 0--- ]
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