GMS84512 Datasheet, PDF (60/123 Pages) Hynix Semiconductor – 8-BIT SINGLE CHIP MICROCOMPUTER

GMS 84512 / 84524
3.6.2 PWM0¡-PWM7 ( 7-bit PWM ¡¿ 8 CH. )
Each PWM0~PWM7 can be used for different PWM output by each 7-bit data register
(PWMR0~PWM7). The PWM pulse period is 1,024§Á and the width is (PWMR+1)¡¿T/128 .
(0<PWMR<127: Value of 7-bit PWM register data)
PWM0~PWM7 is positive, negative for output. The start point of output is spreaded wide,
so the flow of current is proper.
PWM0~PWM7 is port is N-MOS open drain.
¨ç Positive Polarity ( POL2 = 0 )
Pulse Width( 1,024)
)
Pulse Width
¨è Negative Polarity ( POL2 = 1 )
Pulse Period( 1,024 §Á )
Pulse Width
Pulse Width = ( PWMR +1 )£¯128 ¡¿ 1,024 [§Á]
DUTY CYCLE = ( PWMR +1 )£¯128 ¡¿ 100 [ % ]
FIG. 3.6.4 Output Pulse of PWM0 ¡- PWM7
3.6.3 PWMR0¡-PWMR7 REGISTER
PWMR0 ¡-PWMR7 are the data register to define 7-bit PWM pulse width and it has only write
. They are undefined at reset state.
PWMR0 ¡-PWMR7 DATA REGISTER
PWMR0 PWMR1
<00DA_H> <00DB_H>
PWMR2 PWMR3
<00DC_H> <00DD_H>
PWMR4 PWMR5
<00DE_H> <00DF_H>
PWMR6 PWMR7
<00E0_H> <00E1_H>
¦¡
W
W
W
W
W
W
W
7
6
5
4
3
2
1
0
¦¡
PWM0 PWM0 PWM0 PWM0 PWM0 PWM0 PWM0
D6 D5 D4 D3 D2 D1 D0
Initial value (at RESET)
[ Undefined ]
Storage of each PWM data
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