GMS84512 Datasheet, PDF (80/123 Pages) Hynix Semiconductor – 8-BIT SINGLE CHIP MICROCOMPUTER

GMS 84512 / 84524
l Interrupt Request Flag Register ( IRQH, IRQL)
When interupt occurs, interrupt request flag is set. The accepted
interrupt request flag is automatically cleared by interrupt process cycle.
As long as the interrupt request flag which is set to "1" is not
cleared by program, it maintains '1" until interrupt is accepted.
Interrupt Request Flag Register ( IRQH, IRQL) is Read/ Write Register.
So, it is possible to be checked and changed by program.
INTERRUPT REQUEST FLAG REGISTER H, L
IRQH
<00EB_H>
R/W
7
R/W
6
R/W
5
R/W
4
OSDR INT1R INT2R T0R
R/W
3
T2R
R/W
2
R/W
1
1mR ^Vsync
R
R/W
0
T1R
IRQL
<00E9_H>
R/W R/W R/W R/W R/W ¦¡
¦¡
¦¡
7
6
5
4
3
2
1
0
T3R INT3R WDTR BITR SR ¦¡
¦¡
¦¡
Initial Value (At Reset)
[ 0000 0000 ]
Initial Value (At Reset)
[ 0000 0--- ]
Interrupt Request Flag
0 : Disable
1 : Enable
l Interrupt Mode Register ( IMOD)
Interrupt Mode Register determines interrupt priority which can be selected by hardware or
program.
INTERRUPT MODE REGISTER
IMOD
<00E6_H>
¦¡
¦¡ R/W R/W R/W R/W R/W R/W
7
6
5
4
3
2
1
0
¦¡ ¦¡ IM1 IM0 IP3 IP2 IP1 IP0
Initial Value (At Reset)
[ Undefined ]
Interrupt Mode Definition
00 : Mode 0 (Priority by H/W)
01 : Mode 1(Definition by IP3¡-IP0)
1- : Inhibit Interrupt
Interrupt Definition Selection
0000 : ¦¡
1000 : TIMER 1
0001 : OSD
1001 : TIMER 3
0010 : INT1
1010 : INT3
0011 : INT2
1011 : WDT
0100 : TIMER 0 1100 : B.I.T.
0101 : TIMER 2 1101 : SERIAL
0110 : 1024§Á
1110 : ¦¡
0111 : V-SYNC 1111 : ¦¡
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