GMS84512 Datasheet, PDF (43/123 Pages) Hynix Semiconductor – 8-BIT SINGLE CHIP MICROCOMPUTER

GMS 84512 / 84524
l Selection of WDT clock and maximum interval of WDT interrupt
Input clock of WDT is IFBIT, so WDT interval is decided by BTS2~BTS1. Interval of WDT interrupt
become maximum value.
< Notice >
Do not use WDTR=0 for MCU not to be Reset state always.
TABLE 3.2.2 Selection of WDT clock and maximum interval of WDT interrupt
(@ 4MHz)
BTS2
0
0
0
0
1
1
1
1
BTS1
0
0
1
1
0
0
1
1
BTS0
0
1
0
1
0
1
0
1
B.I.T. Input Clock
PS4 ( 2 u S )
PS5 ( 4 u S )
PS6 ( 8 u S )
PS7 ( 16 u S )
PS8 ( 32 u S )
PS9 ( 64 u S )
PS10 ( 128 u S )
PS11 ( 256 u S )
WDT Input Clock
512 uS
1,024 uS
2,048 uS
4,096 uS
8,192 uS
16,384 uS
32,768 uS
65,536 uS
IFWDT max. interval
32,256 uS
64,512 uS
129,024 uS
258,048 uS
516,096 uS
1,032,192 uS
2,064,384 uS
4,128,768 uS
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