GMS84512 Datasheet, PDF (23/123 Pages) Hynix Semiconductor – 8-BIT SINGLE CHIP MICROCOMPUTER

GMS 84512 / 84524
Address
Register Name
SYMBOL R/W ^{RESET VALUE}
7654321 0
00DEH
PWM4 DATA REGISTER
PWMR4 W - _Undefined
00DFH
PWM5 DATA REGISTER
PWMR5 W - _Undefined
00E0H
PWM6 DATA REGISTER
PWMR6 W - _Undefined
00E1H
PWM7 DATA REGISTER
PWMR7 W - _Undefined
00E2H
PWM8 DATA REGISTER HIGH
PWM8H R/W
Undefined
00E3H
PWM8 DATA REGISTER LOW
PWM8L R/W - - _Undefined
00E4H
00E5H
00E6H
00E8H
00E9H
00EAH
00EBH
00ECH
PWM CONTROL REGISTER1
PWM CONTROL REGISTER2
INTERRUPT MODE REGISTER
INTERRUPT ENABLE REGISTER LOW
INTERRUPT REQUEST FLAG REGISTER LOW
INTERRUPT ENABLE REGISTER HIGH
INTERRUPT REQUEST FLAG REGISTER HIGH
INTERRUPT INTERVAL DETERMINATION
CONTROL REGISTER
PWMCR1
PWMCR2
IMOD
IENL
IRQL
IENH
IRQH
IDCR
R/W 0 0 0 0 0 0 0 0
R/W - - - 0 0 0 0 0
R/W - - 0 0 0 0 0 0
R/W 0 0 0 0 0 - - -
R/W 0 0 0 0 0 - - -
R/W 0 0 0 0 0 0 0 0
R/W 0 0 0 0 0 0 0 0
R/W - - - - - 0 0 0
00EDH
00F0H
00F1H
00F2H
00F3H
00F4H
00F5H
00F6H
INTERRUPT INTERVAL DETERMINATION REGISTER IDR
OSD 1st LINE HORIZONTAL POSITION REGISTER
HDP1
OSD 2nd LINE HORIZONTAL POSITION REGISTER HDP2
OSD 3rd LINE HORIZONTAL POSITION REGISTER
HDP3
OSD 1st LINE VERTICAL POSITION REGISTER
VDP1
OSD 2nd LINE VERTICAL POSITION REGISTER
VDP2
OSD 3rd LINE VERTICAL POSITION REGISTER
VDP3
OSD 1st LINE DISPLAY MODE, CHARACTER SIZE,
SMOOTHING FUNCTION SELECTION REGISTER
DMSS1
R 0000000 0
W - - 00000 0
W - - 00000 0
W - - 00000 0
W - 000000 0
W - 000000 0
W - 000000 0
W - 000000 0
00F7H
OSD 2nd LINE DISPLAY MODE, CHARACTER SIZE,
SMOOTHING FUNCTION SELECTION REGISTER
DMSS2
W - 000000 0
00F8H
OSD 3rd LINE DISPLAY MODE, CHARACTER SIZE,
SMOOTHING FUNCTION SELECTION REGISTER
DMSS3
W - 000000 0
00F9H
OSD OUTPUT and BACKGROUND CONTROL
REGISTER
OSDCON1 W 0 0 0 0 0 0 0 0
00FAH
I/O POLARITY CONTROL and OSD OSCILLATION OSDCON2 W 0 0 0 0 0 0 0 0
CONTROL REGISTER
00FCH
OSD RAM ( 2 page ) ACCESSABLE REGISTER
PG2R** R/W
¡ Ø -: Not used *0: READ only for bit 0 *6: READ only for bit 6
¡Ø Write Only Register can not be accessed by bit manipulation instruction.
------- 0
** : OSD RAM area (2-page) can be accessed by LDM,SET1
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