HDM8515 Datasheet, PDF (7/75 Pages) Hynix Semiconductor – DVB/DSS Compliant Receiver

1. Introduction to the HDM8515
The HDM8515 digital demodulator for direct broadcast satellite receivers is a single chip solution fully
compliant with the European Telecommunications Standards Institute (ETSI) specification ETS 300
421. This chip integrates an A/D converter, a variable rate matched filter, a variable rate QPSK
demodulator with a Viterbi decoder, a deinterleaver and a Reed Solomon decoder.
The HDM8515, which is implemented in a 0.25 micron CMOS, Four Layer Metal Process, provides
variable rate capability while operating with a fixed frequency sampling clock. Digital samples of
baseband I and Q data are generated by an internal A/D converter, then provided to the demodulator at
a fixed sample rate. The root raised cosine filter is implemented internally with fully digital techniques.
Similarly, the symbol timing recovery and carrier phase tracking functions are performed entirely in the
digital domain. This approach provides minimum constraints on external circ uits, thus reducing overall
system costs.
The HDM8515 may be configured by an external processor for a specific symbol rate, and carrier
frequency along with loop gain parameters. The HDM8515 provides an external AGC signal which is
used to control the gain of the analog signal which is applied to the down-converters. And it also
provides a digital AGC internally which controls the gain of the signal out of the matched filters. In
addition, the HDM8515 provides fully programmable sweep circuitry to aid in initial acquisition when
large frequency offsets may be present.
The digital frequency translation capability of the HDM8515 permits this part to be used in frequency
multiplexing applications. In this application, an entire transponder bandwidth containing many signals
is sampled at a fixed rate. The digital oscillator within the HDM8515 is programmed to the specific
desired carrier frequency within that band to permit the selected signal to be passed through the
baseband filter and processed by the demodulator circuits.
Reference clk
XTAL1_IN
PLL
C/N
Estimator
Symbol Clock
Viterbi Bit Clock
T ^{AIN_I I}
u
A/D
6
Variable ⁴
Rate
n
e
AIN_Q _Q
Converter
6
QPSK
4
r
Demodulator
WB_AGC
AGC
AGC_Detector
DiSEqC
Interface
I2C
Interface
MCU QPSK
Interface ^Lock
DISEQC
SCL_I2C HI_ADDR[5:0]
SDA_I2C HI_DATA[7:0]
Viterbi
D ecoder
Synchronization
and
8
Deinterleaving
Node
Sync
Viterbi
Data
Frame
Sync
Byte Sync
FIGURE 1: TOP LEVEL BLOCK DIAGRAM
Data Clock
Reed
Solomon
Decoder
DATA_CLK
Data
8
DATA[7:0]
QPSK Lock
QPSK_LOCK
BER
Monitoring
FRAME_SYNC
7