HDM8515 Datasheet, PDF (14/75 Pages) Hynix Semiconductor – DVB/DSS Compliant Receiver

Table 8: Intel 8051 Write Cycle Timing Parameters (Busmode = 1)
Symbol
tsu1
th1
tpw1
tsu2
th2
Parameter
Input Address and Data Setup before /WE Active
Input Address and Data Hold after /WE Inactive
/WE Active Duration
/CE Setup to /WE Active
/CE Hold after /WE Inactive
Min.
Max.
Unit
5
-
ns
5
-
ns
400
-
ns
5
-
ns
5
-
ns
HI_ADDR [4:0]
/CE
/WE
Valid
t_su1
t _h1
tsu2
t_h2
t_pw1
HI_DATA[7:0]
Valid
FIGURE 6: INTEL 8051 WRITE TIMING DIAGRAM
#This page is only for HDM8515P.
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