HDM8515 Datasheet, PDF (22/75 Pages) Hynix Semiconductor – DVB/DSS Compliant Receiver

narrowband AGC which insures that the signal is optimally scaled to the Viterbi decoder to an
accuracy of + or - 0.5 dB to insure optimum FEC performance.
y[k] = Σ h[n] x[k-n]
(1)
In addition to optimizing performance of the Viterbi decoder, the digital narrowband AGC also
insures that the performance of the symbol timing and carrier tracking loops is independent of
signal level variations. An analog wideband AGC is also employed to insure that the analog signal
applied to the A/D converters is properly scaled.
Both the symbol timing and carrier tracking loops are implemented digitally, which eliminates the
need for external connections to analog tuning components during steady state operation. This
causes the requirements on the analog presampling filter to be relaxed, permitting a lower cost
analog front end. For systems which require a narrow band presampling filter, and have the
potential for significant frequency error in the LNB (several MHz) the HDM8515 provides a high
resolution measure of carrier frequency to permit periodic readjustment of the front end tuner
frequency to compensate for drift. The host processor periodically reads the frequency register,
then computes appropriate correction to the tuner frequency.
The nominal symbol rate and the nominal carrier frequency are programmed into the demodulator
to an accuracy provided by 20 bits of resolution, and the system accuracy is equivalent to that of
the fixed frequency sampling clock.
During initial acquisition, the HDM8515 provides an automated sweep program to facilitate carrier
acquisition. The host processor loads a 20 bit register which determines the initial carrier
frequency. A 16 bit register is programmed with the number of symbol times the receiver will dwell
at each frequency. If the receiver remains at the initial frequency for the programmed number of
symbol times without achieving lock, the carrier frequency is incremented by the step frequency
value programmed into another 16 bit register. If no lock is achieved, the receiver will continue to
increment the frequency until the maximum number of search frequencies, as determined by the
value in an 8 register, is achieved. When the max imum number of search frequencies is reached,
the carrier frequency returns to the initial value and the entire process is repeated. Once the host
processor determines that lock is achieved by observing the lock flag, it then inhibits the sweep
function and programs loop bandwidth parameters which are optimized for steady state
performance.
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