HDM8515 Datasheet, PDF (45/75 Pages) Hynix Semiconductor – DVB/DSS Compliant Receiver

5.3 Monitor and Control Interface
Three different modes are supported for the monitor and control interface. Two of the modes are 8
bit parallel interfaces, one which supports Intel microcontrollers and the other intended for Motorola
microcontrollers. The third mode is a serial interface conforming to the I2C standard.
The I2C mode is activated by placing BUSMODE high at the same time both /RE and /WE are low
simultaneously. When this mode is active, the seven bit I2C slave address of the HDM8515 is
configured by the seven least significant bits of the HI_DATA[7:0] bus.
HI_DATA [7:0]
/CE
/RE
/WE
HI_ADDR [4:0]
BUSMODE
DTACK
SCL_I2C
SDA_I2C
SDA_I2CO
SCL_I2CO
This bi-directional data bus is used for transferring control parameters to
the demodulator and for reading the status registers within the
demodulator.
Chip enable is an active low input to the demodulator which signifies that
the other control signals are active.
Read Enable is an active low input to the device which, when active at the
same time chip enable is true, permits the device to drive the HI_DATA
[7:0] lines. When BUSMODE i s 0 (Motorola), this pin is read / not write
(see timing diagrams).
Write enable is an active low input to the device which, when true at the
same time chip enable is true, causes input data on the HI_DATA [7:0] bus
to be transferred to the register defined by the HI_ADDR [4:0] bus. When
BUSMODE is 0 (Motorola), this pin is not data strobe (see timing
diagrams).
The address bus defines which location within the device is to be accessed
during a read or write operation.
BUSMODE selects the type of microcontroller/processor used to setup the
chip. When high, an Intel processor/microcontroller interface is used.
When low, a Motorola processor interface is used.
Data Acknowledge/Data Ready is a tristate output signal which informs
the controlling processor that a data transfer has been acknowledged by
the HDM8515.
This pin provides the clock for the I2C interface when that mode is active.
This pin is the data for the I2C interface and requires an external pull-up
resistor as per the I2C standard.
This pin, which can be by-passed, is the data for the I2C interface.
This pin, which can be by-passed, provides the clock for the I2C interface.
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