HDM8515 Datasheet, PDF (27/75 Pages) Hynix Semiconductor – DVB/DSS Compliant Receiver

The table below illustrates a typical acquisition timing. For this example, the symbol rate is one
half of the clock rate. The code rate is set to 5/6, which requires 13 trial and errors before node
sync is achieved. The carrier search logic requires 10 dwells at different frequencies (500 symbols
per dwell) before demodulator lock is achieved.
Table 12: Example of Acquisition Timing
Carrier Search
Viterbi Node Sync
Byte Sync
Deinterleaver Flush
Reed Solomon
Total Timing
Bit Times
8,333
2,652
16,000
19,584
1,632
48,201
Symbols
5,000
1,591
9,600
11,750
979
26,950
Clock Cycles
10,000
3,182
19,200
23,500
1,958
57,840
The total time required for acquisition could vary widely, depending upon the carrier search range
and the time required for Viterbi node sync. For this example, however, the Byte Sync time and
the time required to flush the deinterleaver dominates the total time. If a 90MHz clock were
employed, the total acquisition time would be 0.642 milliseconds for this example
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