HDM8515 Datasheet, PDF (21/75 Pages) Hynix Semiconductor – DVB/DSS Compliant Receiver

3.2 Variable Rate Demodulator
The block diagram illustrates the overall configuration of the variable rate QPSK demodulator.
Baseband in-phase (I) and quadrature (Q) inputs are applied to the demodulator at a fixed sampling
rate. These digital samples are produced by A/D converters which employ AC coupling to minimize
DC offset.
Signal
Strength
Lock Detect
QPSK Lock
Symbol
Tracking
I_in
Q_in
First
Frequency
Trans.
Dual FIR
NB AGC
Second
Frequency
Trans.
I_out
Q_out
Frequency
Sweeper
Carrier
Tracking
FIGURE 14 DEMODULATOR BLOCK DIAGRAM
The only significant change to this configuration over the HDM8513A is the addition of the Second
Frequency Translator. The carrier tracking block produces two outputs, one is the frequency
correction which is provided to the First Frequency Translator. This insures that the input to the
Dual FIR is always centered at zero frequency error, although there may be a phase error at this
point. The second output of the Carrier Tracking function provides the phase correction to the
Second Frequency Translator.
The carrier frequency error associated with these samples is removed digitally during tracking
operations by a complex multiplier and a digitally controlled oscillator, sometimes called a
numerically controlled oscillator (NCO). During initial acquisition, coarse frequency error is
removed by a combination of the digital AGC within the HDM8515 and external analog tuning
circuits.
A Dual filter performs the root raised cosine filtering of the frequency corrected baseband samples.
This filter, which implements the function of equation (1), is always configured to have an impulse
response duration of 8 symbols regardless of the programmed symbol rate. For low symbol rates,
a large number of samples are used, while for high symbol rates a relatively low number of samples
are processed for each filter output. The outputs of the daul filters are applied to a digital
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