HDM8515 Datasheet, PDF (49/75 Pages) Hynix Semiconductor – DVB/DSS Compliant Receiver

07, 08
09, 0A
0B, 0C
0D
0E
Carrier Loop Filter Control
This field establishes the K1 and K2 gain values for the second order loop
filter of the carrier tracking loop. Bits 0,1,2 and 3 determine the straight-
through gain, and bits 4,5,6 and 7 determine the integration path gain.
The nominal value of this parameter in Hex, is expressed below for
different ranges of symbol rate to clock rate ratios. Two loop filter
configurations are provided at each symbol rate, one for steady state
operation(08) and one which is used only for acquisition(07) to permit
greater frequency pull-in. Initially the gains are set to acquisition values.
When QPSK_LOCK is achieved, they are automatically switched to
steady state values.
Clock/Symbol Rate Steady State Acqu.
2
C7
C7
4
A7
A7
8
87
87
16
67
67
32
47
47
64
27
27
Carrier Sweep Step Size
This 16 bit value defines the size of the step of each carrier frequency
dwell. Bit 7 of address 09 is the MSB and bit 0 of address 0A is the
LSB. The number in this register is divided by 2¹⁶, and multiplied by the
clock frequency to determine the frequency step increment.
Symbols Per Dwell
This 16 bit value defines the time, in symbol periods, for which the
demodulator will dwell before making the next frequency step in a sweep.
Bit 7 of address 0B is the MSB and bit 0 of address 0C is the LSB.
Number of Search Frequencies
This 8 bit field determines the number of frequency steps which occur
during the frequency sweeping process. Combined with the frequency
step size, this determines the frequency span of the carrier sweep.
Narrow Band AGC initial value
This 8 bit field establishes the initial gain of the narrow band AGC. High
numbers correspond to low gain associated with low symbol rates. If the
narrowband AGC function is enabled, this number is used as a starting
point and the closed loop will seek the optimum setting without
processor interaction.
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