HDM8515 Datasheet, PDF (59/75 Pages) Hynix Semiconductor – DVB/DSS Compliant Receiver

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25, 26
Clock Generation PLL Control Parameter-1
Bits [1:0]. VCO range control vector
Default value is 1.
Bits [3:2]. Pre divisor
In case of Extended Frequency mode, this value is used the calculation
of
output Frequency. Default value is 0.
Bit 4. Digital part test mode
When this bit is set to 1and Bit 7 of this register is set to 1, the PLL is
bypassed and the external clock signal is directly connected to the
internal clock. When this bit is set to 0, the generated clock of the PLL
is connected to the internal clock. The default is 1.
Bit 5. VCO power down mode
When this bit is set to 1, VCO power down and does not oscillate
Bit 6. PLL power down mode except VCO
When this bit is set to 1, PLL power down and digital circuits do not
operate and charge pump is disabled.
Bit 7. PLL By-pass
If this bit is set to 0 and Digital part test mode (Bit 4 of this register) is
set to 0, then PLL Normal frequency mode is selected. Else if this bit is
set to 1 and digital part test mode is set to 0, then PLL Extended
frequency mode is selected.
Clock Generation PLL Control Parameter-1
Bits [1:0]. Unused
Bit 2. Counter toggle test
Internal used Only. The default is 0.
Bits [5:3]. Loop filter mode selector
The default is 5H.
Bits [7:6]. Charge pump test mode
Internal used Only. The default is 0.
M Divider Ratio
This 14 bit value defines a feedback divider with a divider ratio M. Bit 5 of
address 25 is the MSB and bit 0 of address 26 is the LSB. The default
value is 002Bh
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