HDM8515 Datasheet, PDF (54/75 Pages) Hynix Semiconductor – DVB/DSS Compliant Receiver

Bit 4. This bit should be fixed to zero
Bit 5. Regulated Data Clock
Enables/Disables the data and data clock regulator. When this bit is set
to 1, data output and data clock are regulated by FIFO operation. When
this bit is set to 0, internal data output and internal data clock are by-
passed
Bit 6. This bit should be fixed to zero.
Bit 7. Clock Polarity
This bit is used to select the DATA_CLK polarity either for serial or
parallel transport interface. If this bit is set to zero(default value), the
transport data and control signals are latched at the positive edge of
DATA_CLK. Otherwise, the signals are latched at the negative edge of
DATA_CLK.
15
Viterbi Lock Threshold
Register 15 to 17 contain control parameters for synchronization in
Viterbi decoder. Ordinary users are recommended to use the default
value.
Bit[7:4] defines the lock threshold for VB_NODESYNC. Viterbi decoder
decides that the correct code rate has been found. A large number
means it takes longer to find the correct code rate in automatic
detection mode. It should be greater than 7. The default value is 12.
Bit[3:0] defines the lock fail threshold. Viterbi decoder rejects a code
rate and moves on to the next code rate. A small number means Viterbi
decoder tries more data before it moves to the next code rate. It should
be less than 7. The default value is 2.
16
Viterbi Unlock Threshold
This number defines the threshold to maintain the Viterbi lock state. A
large number means it needs more bad data to get out of the viterbi lock
state and re-start searching the correct code rate. The default value is
1.
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