HDM8515 Datasheet, PDF (16/75 Pages) Hynix Semiconductor – DVB/DSS Compliant Receiver

Table 10: Motorola Write Cycle Timing Parameters (Busmode =0)
Symbol
tsu1
tsu2
td1
td2
td3
tpw1
th1
th2
Parameter
Data Setup to /DS Active
R/W Setup to /CS and Address
/DS Delay from R/W
DTACK Delay from /DS Active
DTACK Delay from /DS Inactive
/DS Active Duration
Address, /CS and R/W Hold from /DS Inactive
Data Hold from /DS Inactive
Min.
Max.
Unit
5
-
ns
3
-
ns
5
-
ns
-
40
ns
-
10
ns
5
-
ns
5
-
ns
5
-
ns
Valid
HI_ADDR[4:0]
/CS
/DS
R/W
DTACK
HI_DATA[7:0]
tsu2
t_d1
t_pw1
t_h1
t_d2
t_d3
t_su1
t_h2
Valid
FIGURE 8: MOTOROLA WRITE TIMING DIAGRAM
Note: External pull up resistor is required on DTACK.
#This page is only for HDM8515P.
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