HDM8515 Datasheet, PDF (58/75 Pages) Hynix Semiconductor – DVB/DSS Compliant Receiver

1F
Bit 7. This bit should be fixed to zero.
20
Unused
21
Wideband AGC threshold
Bits [5:0]. Wideband AGC threshold
It determines the threshold of wide band AGC accumulator. This value
controls the magnitude of ADC input.
Bit 6. Unused
Bit 7. Wideband AGC Frequency down
It regulates wide band AGC frequency. When this bit is set to zero,
system clock for wide band AGC frequency is sampling clock.
Otherwise, system clock for wide band AGC frequency become sixteen
times of sampling clock frequency.
22
Scaling factor
Bits [2:0]. Scaling factor
This value manages to scale the soft decision demodulator outputs to
the proper levels for the 4 bit soft decision Viterbi inputs. If an overflow is
detected, the output is limited to maximum or minimum 6 bit values.
The upper four bits of this result are passed to the Viterbi decoder.
00H QPSK output
01H QPSK output * 1.25
02H QPSK output * 1.5
03H QPSK output * 1.75
04H QPSK output * 2.00
05H QPSK output * 2.25
06H QPSK output * 2.5
07H QPSK output * 2.75
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